DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 142

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DSPIC33FJ128MC706-I/PT

Manufacturer Part Number
DSPIC33FJ128MC706-I/PT
Description
16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC33FJ128MC706-I/PT

A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
128K Bytes
Ram Size
16K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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dsPIC33F
REGISTER 7-1:
DS70165D-page 140
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-6
bit 5-4
bit 3-2
bit 1-0
R/W-0
CHEN
U-0
CHEN: Channel Enable bit
1 = Channel enabled
0 = Channel disabled
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
DIR: Transfer Direction bit (source/destination bus select)
1 = Read from DMA RAM address, write to peripheral address
0 = Read from peripheral address, write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1 = Initiate block transfer complete interrupt when half of the data has been moved
0 = Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0 = Normal operation
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11 = Reserved (will act as Peripheral Indirect Addressing mode)
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10 = Continuous, Ping-Pong modes enabled
01 = One-Shot, Ping-Pong modes disabled
00 = Continuous, Ping-Pong modes disabled
R/W-0
SIZE
U-0
DMAxCON: DMA CHANNEL x CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
DIR
AMODE<1:0>
R/W-0
R/W-0
HALF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NULLW
R/W-0
U-0
U-0
U-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
MODE<1:0>
R/W-0
U-0
bit 8
bit 0

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