DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 185

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.12.4
Each of the Fault input pins have two modes of
operation:
• Latched Mode: When the Fault pin is driven low,
• Cycle-by-Cycle Mode: When the Fault input pin
The operating mode for each Fault input pin is selected
using the FLTAM and FLTBM control bits in the
FLTACON and FLTBCON Special Function Registers.
Each of the Fault pins can be controlled manually in
software.
15.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the PWM Time
Base Period register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS control bit in the PWMCON2 SFR. The UDIS
bit affects all Duty Cycle Buffer registers and the PWM
Time Base Period register, PTPER. No duty cycle
changes or period value changes will have effect while
UDIS = 1.
If the IUE bit is set, any change to the Duty Cycle
registers will be immediately updated regardless of the
UDIS bit state. The PWM Period register (PTPER)
updates are not affected by the IUE control bit.
© 2006 Microchip Technology Inc.
the PWM outputs will go to the states defined in
the FLTACON/FLTBCON registers. The PWM
outputs will remain in this state until the Fault pin
is driven high and the corresponding interrupt flag
has been cleared in software. When both of these
actions have occurred, the PWM outputs will
return to normal operation at the beginning of the
next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the Fault condition
ends, the PWM module will wait until the Fault pin
is no longer asserted, to restore the outputs.
is driven low, the PWM outputs remain in the
defined Fault states for as long as the Fault pin is
held low. After the Fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
FAULT INPUT MODES
Preliminary
15.14 PWM Special Event Trigger
The PWM module has a Special Event Trigger that
allows ADC conversions to be synchronized to the
PWM time base. The ADC sampling and conversion
time may be programmed to occur at any point within
the PWM period. The Special Event Trigger allows the
user to minimize the delay between the time when ADC
conversion results are acquired and the time when the
duty cycle value is updated.
The PWM Special Event Trigger has an SFR named
SEVTCMP, and five control bits to control its operation.
The PTMR value for which a Special Event Trigger
should occur is loaded into the SEVTCMP register.
When the PWM time base is in an Up/Down Count
mode, an additional control bit is required to specify the
counting phase for the Special Event Trigger. The
count phase is selected using the SEVTDIR control bit
in the SEVTCMP SFR. If the SEVTDIR bit is cleared,
the Special Event Trigger will occur on the upward
counting cycle of the PWM time base. If the SEVTDIR
bit is set, the Special Event Trigger will occur on the
downward count cycle of the PWM time base. The
SEVTDIR control bit has no effect unless the PWM
time base is configured for an Up/Down Count mode.
15.14.1
The PWM Special Event Trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON2 SFR.
The special event output postscaler is cleared on the
following events:
• Any write to the SEVTCMP register
• Any device Reset
15.15 PWM Operation During CPU Sleep
The Fault A and Fault B input pins have the ability to
wake the CPU from Sleep mode. The PWM module
generates an interrupt if either of the Fault pins is
driven low while in Sleep.
15.16 PWM Operation During CPU Idle
The PTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters Idle mode. If
PTSIDL = 0, the module will continue to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in Idle mode.
Mode
Mode
SPECIAL EVENT TRIGGER
POSTSCALER
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