DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 260

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DSPIC33FJ128MC706-I/PT

Manufacturer Part Number
DSPIC33FJ128MC706-I/PT
Description
16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC33FJ128MC706-I/PT

A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
128K Bytes
Ram Size
16K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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dsPIC33F
REGISTER 20-28: CiTRBnDLC: ECAN BUFFER n DATA LENGTH CONTROL (n = 0, 1, ..., 31)
REGISTER 20-29: CiTRBnDm: ECAN BUFFER n DATA FIELD BYTE m (n = 0, 1, ..., 31; m = 0, 1, ..., 7)
DS70165D-page 258
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9
bit 8
bit 7-5
bit 4
bit 3-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
TRBnDm7
R/W-x
R/W-x
EID5
U-0
The Most Significant Byte contains byte (m + 1) of the buffer.
EID<5:0>: Extended Identifier bits
RTR: Remote Transmission Request bit
1 = Message will request remote transmission
0 = Normal message
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
Unimplemented: Read as ‘0’
RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
DLC<3:0>: Data Length Code bits
TRnDm<7:0>: Data Field Buffer ‘n’ Byte ‘m’ bits
TRBnDm6
R/W-x
R/W-x
EID4
U-0
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRBnDm5
R/W-x
R/W-x
EID3
U-0
TRBnDm4
R/W-x
R/W-x
R/W-x
EID2
RB0
Preliminary
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
TRBnDm3
R/W-x
R/W-x
R/W-x
DLC3
EID1
TRBnDm2
R/W-x
R/W-x
R/W-x
DLC2
EID0
© 2006 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
TRBnDm1
R/W-x
R/W-x
R/W-x
DLC1
RTR
TRBnDm0
R/W-x
R/W-x
R/W-x
DLC0
RB1
bit 8
bit 0
bit 0
(1)

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