DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 277

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

22.0
The dsPIC33F devices have up to 32 ADC input chan-
nels. These devices also have up to 2 ADC modules
(ADCx, where ‘x’ = 1 or 2), each with its own set of
Special Function Registers.
The AD12B bit (ADxCON1<10>) allows each of the
ADC modules to be configured by the user as either a
10-bit, 4-sample/hold ADC (default configuration) or a
12-bit, 1-sample/hold ADC.
22.1
The 10-bit ADC configuration has the following key
features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 32 analog input pins
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
• Operation during CPU Sleep and Idle modes
The 12-bit ADC configuration supports all the above
features, except:
• In the 12-bit configuration, conversion speeds of
• There is only 1 sample/hold amplifier in the 12-bit
Depending on the particular device pinout, the ADC
can have up to 32 analog input pins, designated AN0
through AN31. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs may be shared with other ana-
log input pins. The actual number of analog input pins
and external voltage reference input configuration will
depend on the specific device. Refer to the device data
sheet for further details.
A block diagram of the ADC is shown in Figure 22-1.
© 2006 Microchip Technology Inc.
Note:
Note:
pins
fractional/integer)
up to 500 ksps are supported
configuration, so simultaneous sampling of
multiple channels is not supported.
10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
Key Features
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
The ADC module needs to be disabled
before modifying the AD12B bit.
Preliminary
22.2
The following configuration steps should be performed.
1.
2.
22.3
If more than one conversion result needs to be buffered
before triggering an interrupt, DMA data transfers can
be used. Both ADC1 and ADC2 can trigger a DMA data
transfer. If ADC1 or ADC2 is selected as the DMA IRQ
source, a DMA transfer occurs when the AD1IF or
AD2IF bit gets set as a result of an ADC1 or ADC2
sample conversion sequence.
The SMPI<3:0> bits (ADxCON2<5:2>) are used to
select how often the DMA RAM buffer pointer is
incremented.
The ADDMABM bit (ADxCON1<12>) determines how
the conversion results are filled in the DMA RAM buffer
area being used for ADC. If this bit is set, DMA buffers
are written in the order of conversion. The module will
provide an address to the DMA channel that is the
same as the address used for the non-DMA
stand-alone buffer. If the ADDMABM bit is cleared,
then DMA buffers are written in Scatter/Gather mode.
The module will provide a scatter/gather address to the
DMA channel, based on the index of the analog input
and the size of the DMA buffer.
Configure the ADC module:
a)
b)
c)
d)
e)
f)
g)
Configure ADC interrupt (if required):
a)
b)
ADC Initialization
Select
(ADxPCFGH<15:0> or ADxPCFGL<15:0>)
Select voltage reference source to match
expected
(ADxCON2<15:13>)
Select the analog conversion clock to
match desired data rate with processor
clock (ADxCON3<5:0>)
Determine how many S/H channels will
be
ADxPCFGH<15:0> or ADxPCFGL<15:0>)
Select the appropriate sample/conversion
sequence
ADxCON3<12:8>)
Select
presented in the buffer (ADxCON1<9:8>)
Turn on ADC module (ADxCON1<15>)
Clear the ADxIF bit
Select ADC interrupt priority
ADC and DMA
used
port
how
range
pins
(ADxCON1<7:5>
conversion
(ADxCON2<9:8>
dsPIC33F
on
as
DS70165D-page 275
analog
analog
results
inputs
inputs
and
and
are