DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 364

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Instruction-Based Power-Saving Modes ........................... 157
Internal RC Oscillator
Internet Address................................................................ 365
Interrupt Control and Status Registers................................ 91
Interrupt Setup Procedures ............................................... 133
Interrupt Vector Table (IVT) ................................................ 87
Interrupts Coincident with Power Save Instructions.......... 158
J
JTAG Boundary Scan Interface ........................................ 289
M
Memory Organization.......................................................... 39
Microchip Internet Web Site .............................................. 365
Modes of Operation
Modulo Addressing ............................................................. 68
Motor Control PWM .......................................................... 175
Motor Control PWM Module
MPLAB ASM30 Assembler, Linker, Librarian ................... 306
MPLAB ICD 2 In-Circuit Debugger ................................... 307
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment
MPLAB PM3 Device Programmer .................................... 307
MPLINK Object Linker/MPLIB Object Librarian ................ 306
N
NVM Module
O
Open-Drain Configuration ................................................. 160
Output Compare ............................................................... 171
P
Packaging ......................................................................... 351
Peripheral Module Disable (PMD) .................................... 158
© 2006 Microchip Technology Inc.
Idle ............................................................................ 158
Sleep......................................................................... 157
Use with WDT ........................................................... 294
IECx ............................................................................ 91
IFSx............................................................................. 91
INTCON1 .................................................................... 91
INTCON2 .................................................................... 91
IPCx ............................................................................ 91
Initialization ............................................................... 133
Interrupt Disable........................................................ 133
Interrupt Service Routine .......................................... 133
Trap Service Routine ................................................ 133
Disable ...................................................................... 233
Initialization ............................................................... 233
Listen All Messages .................................................. 233
Listen Only ................................................................ 233
Loopback .................................................................. 233
Normal Operation...................................................... 233
Applicability ................................................................. 70
Operation Example ..................................................... 69
Start and End Address................................................ 69
W Address Register Selection .................................... 69
8-Output Register Map................................................ 52
In-Circuit Emulator .................................................... 307
In-Circuit Emulator .................................................... 307
Software.................................................................... 305
Register Map............................................................... 66
Registers................................................................... 174
Details ....................................................................... 352
Marking ..................................................................... 351
Preliminary
PICSTART Plus Development Programmer..................... 308
Pinout I/O Descriptions (table)............................................ 25
PMD Module
POR and Long Oscillator Start-up Times ........................... 86
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Power-Saving Features .................................................... 157
Program Address Space..................................................... 39
Program Memory
Pulse-Width Modulation Mode.......................................... 172
PWM
PWM Dead-Time Generators ........................................... 180
PWM Duty Cycle
PWM Fault Pins ................................................................ 182
Register Map .............................................................. 66
Register Map .............................................................. 64
Register Map .............................................................. 64
Register Map .............................................................. 65
Register Map .............................................................. 65
Register Map .............................................................. 65
Register Map .............................................................. 65
Register Map .............................................................. 66
Clock Frequency and Switching ............................... 157
Construction ............................................................... 72
Data Access from Program Memory Using
Data Access from Program Memory Using
Data Access from, Address Generation ..................... 73
Memory Map............................................................... 39
Table Read Instructions
Visibility Operation...................................................... 75
Interrupt Vector........................................................... 40
Organization ............................................................... 40
Reset Vector............................................................... 40
Center-Aligned.......................................................... 179
Complementary Mode .............................................. 180
Complementary Output Mode .................................. 181
Duty Cycle ................................................................ 172
Edge-Aligned ............................................................ 178
Independent Output Mode........................................ 181
Operation During CPU Idle Mode............................. 183
Operation During CPU Sleep Mode ......................... 183
Output Override ........................................................ 181
Output Override Synchronization ............................. 182
Period ............................................................... 172, 178
Single Pulse Mode.................................................... 181
Assignment ............................................................... 181
Ranges ..................................................................... 181
Selection Bits (table)................................................. 181
Comparison Units ..................................................... 179
Immediate Updates .................................................. 179
Register Buffers........................................................ 179
Enable Bits ............................................................... 182
Fault States .............................................................. 182
Input Modes.............................................................. 183
Table Instructions ............................................... 74
TBLRDH ............................................................. 74
TBLRDL.............................................................. 74
Cycle-by-Cycle ................................................. 183
Latched............................................................. 183
Program Space Visibility.................................... 75
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