DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 88

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33F
TABLE 5-3:
5.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
5.2.2
If the FSCM is enabled, it begins to monitor the system
clock source when SYSRST is released. If a valid clock
source is not available at this time, the device auto-
matically switches to the FRC oscillator and the user
can switch to the desired crystal oscillator in the Trap
Service Routine.
DS70165D-page 86
POR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
2:
3:
4:
5:
6:
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode, only if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
POR AND LONG OSCILLATOR
START-UP TIMES
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
STARTUP
OST
POR
RST
LOCK
FSCM
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Internal state Reset time (20 s nominal).
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 s nominal).
= Fail-Safe Clock Monitor delay (100 s nominal).
Any Clock
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
= Conditional POR delay of 20 s nominal (if on-chip regulator is enabled) or 64 ms nominal
Clock Source
T
T
T
T
POR
POR
POR
POR
SYSRST Delay
+ T
+ T
+ T
+ T
Preliminary
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
STARTUP
+ T
+ T
+ T
+ T
particular value at a device Reset. The SFRs are
5.2.2.1
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, T
matically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 100 s and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
5.3
Most of the Special Function Registers (SFRs) associ-
ated with the CPU and peripherals are reset to a
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of two registers. The
Reset value for the Reset Control register, RCON,
depends on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, depends
on the type of Reset and the programmed values of the
oscillator Configuration bits in the FOSC Configuration
register.
RST
RST
RST
RST
is also applied to all returns from powered-down
Special Function Register Reset
States
System Clock
T
OST
FSCM Delay for Crystal and PLL
Clock Sources
T
Delay
T
LOCK
+ T
—
OST
—
—
—
—
—
—
LOCK
© 2006 Microchip Technology Inc.
FSCM
T
T
T
Delay
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3
3
3
3
3
FSCM
Notes
, is auto-