PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet

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PIC24FJ256GB206-I/MR

Manufacturer Part Number
PIC24FJ256GB206-I/MR
Description
16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC24FJ256GB206-I/MR

A/d Inputs
16 Channel, 10-bit
Comparators
3
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
52
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin QFN
Programmable Memory
256K Bytes
Ram Size
98K Bytes
Speed
32 MHz
Temperature Range
–40 to 85 °C
Timers
5-16-bit
Voltage, Range
2.2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
PIC24FJ256GB210 Family
Data Sheet
64/100-Pin,
16-Bit Flash Microcontrollers
with USB On-The-Go (OTG)
 2010 Microchip Technology Inc.
DS39975A

Related parts for PIC24FJ256GB206-I/MR

PIC24FJ256GB206-I/MR Summary of contents

Page 1

... PIC24FJ256GB210 Family  2010 Microchip Technology Inc. Data Sheet 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) 64/100-Pin, DS39975A ...

Page 2

... MCUs and dsPIC ® devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. logo, MPLAB, PIC, PICmicro, PICSTART, DSCs code hopping ® ®  2010 Microchip Technology Inc. ...

Page 3

... chip select lines - Acknowledgement lines (one per chip select) - Programmable address/data multiplexing - Programmable address and data Wait states - Programmable polarity on control signals PIC24FJ Device PIC24FJ128GB206 64 128K PIC24FJ256GB206 64 256K PIC24FJ128GB210 100/121 128K PIC24FJ256GB210 100/121 256K  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Peripheral Features (Continued): • ...

Page 4

... In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words  2010 Microchip Technology Inc. ...

Page 5

... AN2/C2INB/VMIO/RP13/CN4/RB2 14 PGEC1/AN1/V -/RP1/CN3/RB1 REF 15 PGED1/AN0/V +/PMA6/RP0/CN2/RB0 REF 16 Note 1: The back pad on QFN devices should be connected to V Legend: RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant +5.5V.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY PIC24FJXXXGB206 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/ ...

Page 6

... SCL1/RP3/PMA15/PMCS2 /CN55/RD10 (1) 45 RP12/PMA14/PMCS1 /CN56/RD11 46 DMH/RP11/INT0/CN49/RD0 47 SOSCI/C3IND/CN1/RC13 48 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 49 V /RP24/V /CN50/RD1 CPCON BUSCHG 50 DPH/RP23/PMACK1/CN51/RD2 51 RP22/PMBE0/CN52/RD3 52 RP25/PMWR/CN13/RD4 53 RP20/PMRD/CN14/RD5 54 C3INB/CN15/RD6 55 C3INA/SESSEND/CN16/RD7 56 V CAP 57 ENVREG 1/V /CN68/RF0 BUSST CMPST BUSVLD 59 V 2/SESSVLD/CN69/RF1 CMPST 60 PMD0/CN58/RE0 61 PMD1/CN59/RE1 62 PMD2/CN60/RE2 63 PMD3/CN61/RE3 64 PMD4/CN62/RE4  2010 Microchip Technology Inc. ...

Page 7

... PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 21 AN3/C2INA/VPIO/CN5/RB3 22 AN2/C2INB/VMIO/RP13/CN4/RB2 23 PGEC1/AN1/V -/RP1/CN3/RB1 REF 24 PGED1/AN0/V +/RP0/CN2/RB0 REF 25 Legend: RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant +5.5V.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY PIC24FJXXXGB210 SOSCO/SCLKI/TICK/C3INC/ 74 RPI37/CN0/RC14 73 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 72 RP12/PMA14/PMCS1/CN56/RD11 71 RP3/PMA15/PMCS2/CN55/ 70 RD10 DPLN/RP4/PMACK2/CN54/ ...

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... TDI/PMA21/PMA3 61 TDO/CN38/RA5 OSCI/CLKI/CN23/RC12 63 64 OSCO/CLKO/CN22/RC15 SCL1/RPI36/PMA22/PMCS2 67 SDA1/RPI35/PMBE1/CN44/RA15 68 DMLN/RTCC/RP2/CN53/RD8 69 DPLN/RP4/PMACK2/CN54/RD9 70 RP3/PMA15/PMCS2 71 RP12/PMA14/PMCS1 72 DMH/RP11/INT0/CN49/RD0 73 SOSCI/C3IND/CN1/RC13 74 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 /RP24/V CPCON 77 DPH/RP23/PMACK1/CN51/RD2 78 RP22/PMBE0/CN52/RD3 79 RPI42/PMD12/CN57/RD12 80 PMD13/CN19/RD13 + and V - when the ALTVREF Configuration bit is programmed. REF Function (2) /CN36/RA3 (2) /CN37/RA4 (2) /CN43/RA14 (3) /CN55/RD10 (3) /CN56/RD11 /CN50/RD1 BUSCHG  2010 Microchip Technology Inc. ...

Page 9

... Note 1: Alternate pin assignments for V REF 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Pin 91 AN23/CN39/RA6 92 AN22/PMA17/CN40/RA7 93 PMD0/CN58/RE0 ...

Page 10

... RD3 V RC14 SS RD4 RC13 RD11 V DD RD0 n/c RD10 RD9 RD8 RA14 V OSCI/ V OSCO RC12 RC15 N/C RA5 RA4 RA3 /RF7 V D+/RG2 RA2 USB N/C N/C RF8 D-/RG3 V RD15 USBID/ RF2 DD RF3 RD14 RF4 RF5  2010 Microchip Technology Inc. ...

Page 11

... RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Note 1: Alternate pin assignments for V REF 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Pin PMD9/CN78/RG1 E7 ...

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... Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’. DS39975A-page 12 Pin L1 PGEC2/AN6/RP6/CN24/RB6 ( /PMA7/CN41/RA9 REF L3 AVSS L4 AN9/RP9/CN27/RB9 L5 AN10/CV REF L6 RP31/CN76/RF13 L7 AN13/PMA10/CTEDG1/CN31/RB13 L8 AN15/REFO/RP29/PMA0/CN12/RB15 L9 RPI43/CN20/RD14 L10 RP10/PMA9/CN17/RF4 L11 RP17/PMA8/SCL2/CN18/RF5 — — — + and V - when the ALTVREF Configuration bit is programmed. REF Function /PMA13/CN28/RB10 — — —  2010 Microchip Technology Inc. ...

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... Electrical Characteristics .......................................................................................................................................................... 347 30.0 Packaging Information.............................................................................................................................................................. 363 Appendix A: Revision History............................................................................................................................................................. 375 Index ................................................................................................................................................................................................. 377 The Microchip Web Site ..................................................................................................................................................................... 383 Customer Change Notification Service .............................................................................................................................................. 383 Customer Support .............................................................................................................................................................................. 383 Reader Response .............................................................................................................................................................................. 384 Product Identification System ............................................................................................................................................................ 385  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY DS39975A-page 13 ...

Page 14

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39975A-page 14  2010 Microchip Technology Inc. ...

Page 15

... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ128GB206 • PIC24FJ256GB206 • PIC24FJ128GB210 • PIC24FJ256GB210 The PIC24FJ256GB210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a large data RAM Kbytes. The PIC24FJ256GB210 family allows the CPU to fetch data directly from an external memory device using the EPMP module ...

Page 16

... This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. pins (29 pins on pin features available on the  2010 Microchip Technology Inc. ...

Page 17

... Ports (28 I/O, 1 Input only) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP and QFN PIC24FJ256GB206 256K 87,552 96K 52 ( (1) 9 (1) ...

Page 18

... Yes Yes 24 3 Yes Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP and 121-Pin BGA  2010 Microchip Technology Inc. 256K 87,552 ...

Page 19

... Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count. 2: These peripheral I/Os are only accessible through remappable pins.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Data Bus Data Latch ...

Page 20

... F2 I ANA Comparator 2 Input ANA Comparator 3 Input ANA Comparator 3 Input B. B11 I ANA Comparator 3 Input C. C10 I ANA Comparator 3 Input Main Clock Input Connection. F11 O — System Clock Output Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 21

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 22

... ALTVREF (CW1<5>) bit is programmed to ‘0’. REF DS39975A-page 22 Input I/O 121-Pin Buffer BGA E11 A11 I ST A10 E10 I ST D11 I ST C11 Interrupt-on-Change Inputs K11 I ST K10 J10 Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 23

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 24

... Parallel Master Port Byte Enable Strobe 1. (3) C11 ,G1 I/O ST/TTL Parallel Master Port Chip Select Strobe 1. (2) D11 ,E1, O — Parallel Master Port Chip Select Strobe 2. (1) E11 ST = Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 25

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 26

... ST J3 I/O ST PORTB Digital I/ I/O ST PORTC Digital I/O. F9 I/O ST C10 I/O ST B11 I/O ST F11 I USB Receive Input (from external transceiver Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 27

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 28

... PORTG Digital I/ I/O ST D11 I/O ST E10 I/O ST Remappable Peripheral (input or output). L10 I I/O ST C11 I I I/O ST J10 I/O ST K10 I/O ST L11 Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 29

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 30

... A/D and Comparator Reference Voltage (high) Input. B10, F5, P — Ground Reference for Logic and I/O Pins. F10, G6, G7, H3, D4 — USB Voltage (3.3V Schmitt Trigger input buffer C™ C/SMBus input buffer Description Charge Output. BUS PWM/Charge Output.  2010 Microchip Technology Inc. ...

Page 31

... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 2- MCLR C1 PIC24FXXXX V SS ...

Page 32

... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL  2010 Microchip Technology Inc. ...

Page 33

... The placement of this capacitor should be close recommended that the trace length not CAP exceed 0.25 inch (6 mm). Refer to Section 29.0 “Electrical Characteristics” for information.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 2- 0.1 0.01 pin must not CAP 0.001 ...

Page 34

... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSCI ` OSCO GND ` SOSCO SOSC I ` Sec Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1  2010 Microchip Technology Inc. ...

Page 35

... Microchip Technology Inc. PIC24FJ256GB210 FAMILY If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: • ...

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... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 36  2010 Microchip Technology Inc. ...

Page 37

... All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY The core supports Inherent (no operand), Relative, Literal, Memory Direct Addressing modes along with three groups of addressing modes ...

Page 38

... ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Repeat Loop Counter Register CPU Control Register Disable Interrupt Count Register Data Space Read Page Register Data Space Write Page Register Peripheral Modules  2010 Microchip Technology Inc. ...

Page 39

... FIGURE 3-2: PROGRAMMER’S MODEL W0 (WREG) Divider Working Registers Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Frame Pointer Stack Pointer SPLIM TBLPAG 9 DSRPAG 8 DSWPAG ...

Page 40

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th low-order bit (for byte-sized data low-order bit of the result has occurred (1,2) U-0 U-0 R/W-0, HSC — — DC bit bit Bit is unknown th low-order bit (for word-sized data)  2010 Microchip Technology Inc. ...

Page 41

... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — ...

Page 42

... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided in Table 3-2. Description  2010 Microchip Technology Inc. ...

Page 43

... FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB210 FAMILY DEVICES Note: Memory areas are not shown to scale.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces” ...

Page 44

... Device PIC24FJ128GB2XX PIC24FJ256GB2XX least significant word Instruction Width Word for devices in the FLASH CONFIGURATION WORDS FOR PIC24FJ256GB210 FAMILY DEVICES Program Configuration Word Memory Addresses (Words) 44,032 0x0157F8:0x0157FE 87,552 0x02ABF8:0x02ABFE PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006  2010 Microchip Technology Inc. ...

Page 45

... PIC24FJXXXGB206 96 Kbytes (30K + 66K Note 1: The internal RAM above 30 Kbytes can be accessed through the EDS window.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY The EDS includes any additional internal data memory not accessible by the lower 32-Kbyte data address space and any external memory through EPMP. For more details on accessing internal extended data memory, refer to the “ ...

Page 46

... EDS Page 0x300 FFFEh EDS Page 0x3FF (1) Near Data Space Internal Extended Data RAM(66 Kbytes) EPMP Memory Space Program Space Visibility Area to Access Lower Word of Program Memory Program Space Visibility Area to Access Upper Word of Program Memory  2010 Microchip Technology Inc. ...

Page 47

... EPMP RTC/Comp 700h — — Legend: — = There are no implemented SFRs in this block  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. ® MCUs and Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words ...

Page 48

TABLE 4-4: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...

Page 49

TABLE 4-5: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE (1) (1) (1) (1) CNPD3 005A CN47PDE CN46PDE CN45PDE CN44PDE CN43PDE CNPD4 ...

Page 50

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...

Page 51

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 IPC18 00C8 — — — — IPC19 00CA — — — — IPC20 00CC — U3TXIP2 ...

Page 52

TABLE 4-8: INPUT CAPTURE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IC1CON1 0140 — — ICSIDL ICTSEL2 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ICTSEL2 IC2CON2 ...

Page 53

TABLE 4-9: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A — — OCSIDL ...

Page 54

TABLE 4-9: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC8CON1 01D6 — — OCSIDL OCTSEL2 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 — — ...

Page 55

TABLE 4-11: UART REGISTER MAPS File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...

Page 56

TABLE 4-12: SPI REGISTER MAPS File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — SPI1BUF 0248 SPI2STAT 0260 SPIEN — ...

Page 57

TABLE 4-15: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02D0 TRISC15 TRISC14 TRISC13 TRISC12 (2,3) (2) PORTC 02D2 RC15 RC14 RC13 RC12 LATC 02D4 LATC15 LATC14 LATC13 LATC12 ODCC 02D6 ODC15 ODC14 ...

Page 58

TABLE 4-18: PORTF REGISTER MAP File (1) (1) Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISF 02E8 — — TRISF13 TRISF12 PORTF 02EA — — RF13 RF12 LATF 02EC — — LATF13 LATF12 ODCF 02EE — — ...

Page 59

TABLE 4-21: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...

Page 60

TABLE 4-21: ADC REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name AD1CON1 0320 ADON — ADSIDL — AD1CON2 0322 VCFG2 VCFG1 VCFG0 r AD1CON3 0324 ADRC r r SAMC4 AD1CHS 0328 CH0NB — — ...

Page 61

TABLE 4-23: USB OTG REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (2) U1OTGIR 0480 — — — — (2) U1OTGIE 0482 — — — — 2) U1OTGSTAT 0484 — — — — (2) U1OTGCON ...

Page 62

TABLE 4-23: USB OTG REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1EP10 04BE — — — — U1EP11 04C0 — — — — U1EP12 04C2 — — — — U1EP13 04C4 — — ...

Page 63

TABLE 4-26: ENHANCED PARALLEL MASTER/SLAVE PORT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name PMCON1 0600 PMPEN — PSIDL ADRMUX1 PMCON2 0602 BUSY — ERROR TIMEOUT PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN PMCON4 0606 PTEN15 ...

Page 64

TABLE 4-28: COMPARATORS REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CMSTAT 0630 CMIDL — — — CVRCON 0632 — — — — CM1CON 0634 CON COE CPOL — CM2CON 0636 CON COE CPOL — ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — INT1R5 INT1R4 RPINR1 0682 — — INT3R5 INT3R4 RPINR2 0684 — — — — RPINR3 0686 — — ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — RP1R5 RP1R4 RPOR1 06C2 — — RP3R5 RP3R4 (1) (1) RPOR2 06C4 — — RP5R5 RP5R4 RPOR3 ...

Page 67

TABLE 4-31: SYSTEM REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — — ...

Page 68

... EPMP EPMP 0x7FFFFE 0x01FFFE 0xFFFFFE 0x007FFE DSRPAG DSxPAG DSx PAG DSRPAG = 0x2FF = 0x003 = 0x1FF = 0x200 Data Space Write register 0x000001 0x7F8001 Program Program Space Space Access Access 0x007FFF 0x7FFFFF DSRPAG DSRPAG = 0x300 = 0x3FF Program Memory  2010 Microchip Technology Inc. ...

Page 69

... Double - word from the selected location mov.d [w1 ;two word read, stored in w2 and w3  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed EDS location can be read. ...

Page 70

... EDS window is enabled by setting bit 15 of the working register, assigned with the offset address, and the accessed location can be written. Figure 4-2 illustrates how the EDS space address is generated for write operations Bits 24-Bit EA Wn<0> is Byte Select  2010 Microchip Technology Inc. ...

Page 71

... This data space can also be accessed by Direct Addressing. 3: When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is ‘0’, an address error trap will occur.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Note 1: All write operations to EDS are executed in a single cycle. 2: Use of a Read/Modify/Write operation on any EDS location under a REPEAT instruction is not supported ...

Page 72

... Table 4-35 and Figure 4-8 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.  2010 Microchip Technology Inc. ...

Page 73

... The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table read operations are permitted in the configuration memory space.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Program Space Address < ...

Page 74

... TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 800000h Only read operations are shown; write operations are also valid in the user memory area. Data EA<15:0>  2010 Microchip Technology Inc. ...

Page 75

... Note 1: When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is ‘0’, an address error trap will occur.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Table 4-36 provides the corresponding 23-bit EDS address for program memory with EDS page and source addresses. ...

Page 76

... Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the FFFFh EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program space address.  2010 Microchip Technology Inc. ...

Page 77

... Double - word from the selected location mov.d [w1  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY ;page 0x202, consisting lower words, is selected for read ;select the location (0x0A read ;set the MSB of the base address, enable EDS mode ;read Low byte ...

Page 78

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 78  2010 Microchip Technology Inc. ...

Page 79

... Counter Using Table Instruction User/Configuration Space Select  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- Manual” ...

Page 80

... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the opera- tion and the WR bit is automatically cleared when the operation is finished.  2010 Microchip Technology Inc. ...

Page 81

... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only; refer to the device programming specification.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY (1) U-0 U-0 — — ...

Page 82

... Initialize in-page EA<15:0> pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted  2010 Microchip Technology Inc. ...

Page 83

... BSET NVMCON, #WR NOP NOP BTSC NVMCON, #15 BRA $-2  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...

Page 84

... Data to program upper byte // Initialize NVMCON // Initialize PM Page Boundary SFR // Initialize lower word of address // Write to address low word // Write to upper byte // Block interrupts with priority <7 // for next 5 instructions // C30 function to perform unlock // sequence and set WR  2010 Microchip Technology Inc. ...

Page 85

... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...

Page 86

... R/W-0, HS R/W-0, HS R/W-0, HS (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (2) U-0 R/W-0, HS R/W-0 (3) — CM VREGS bit 8 R/W-1, HS R/W-1, HS BOR POR bit Bit is unknown , when waking up from VREG  2010 Microchip Technology Inc. ...

Page 87

... PWRSAV #0 Instruction IDLE (RCON<2>) PWRSAV #1 Instruction BOR (RCON<1>) POR, BOR POR (RCON<0>) POR Note: All Reset flag bits may be set or cleared by the user software.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY (1) (CONTINUED) VREG Setting Event , when waking up from Clearing Event POR ...

Page 88

... Refer to Section 8.0 “Oscillator Configuration” for further details. TABLE 6-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Reset Type Clock Source Determinant POR FNOSC Configuration bits (CW2<10:8>) BOR MCLR COSC Control bits WDTO (OSCCON<14:12>) SWR  2010 Microchip Technology Inc. ...

Page 89

... RC Oscillator start-up times. FRC LPRC 7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC so the system clock delay is just T primary oscillator after its respective clock delay.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY System Clock SYSRST Delay ...

Page 90

... If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR).  2010 Microchip Technology Inc. ...

Page 91

... PIC24FJ256GB210 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. The ALTIVT (INTCON2< ...

Page 92

... Alternate Interrupt Vector Table (AIVT) 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 000112h Reserved (1) (1) Trap Source  2010 Microchip Technology Inc. ...

Page 93

... Output Compare 8 Output Compare 9 Enhanced Parallel Master Port (EPMP) Real-Time Clock and Calendar (RTCC) SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Vector IVT AIVT Number Address Address 13 00002Eh 00012Eh IFS0< ...

Page 94

... IEC0<3> IPC0<14:12> IEC0<7> IPC1<14:12> IEC0<8> IPC2<2:0> IEC1<11> IPC6<14:12> IEC1<12> IPC7<2:0> IEC4<1> IPC16<6:4> IEC0<11> IPC2<14:12> IEC0<12> IPC3<2:0> IEC4<2> IPC16<10:8> IEC1<14> IPC7<10:8> IEC1<15> IPC7<14:12> IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> IEC5<7> IPC21<14:12> IEC5<8> IPC22<2:0> IEC5<9> IPC22<6:4> IEC5<6> IPC21<10:8>  2010 Microchip Technology Inc. ...

Page 95

... The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY a generic ISR is used for multiple vectors (such as when ISR remapping is used in bootloader applica- tions check if another interrupt is pending while in an ISR ...

Page 96

... U-0 R/C-0, HSC r-1 (1) — IPL3 Clearable bit HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown (1) U-0 U-0 — — bit 8 U-0 U-0 — — bit 0  2010 Microchip Technology Inc. ...

Page 97

... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — ...

Page 98

... Interrupt on positive edge DS39975A-page 98 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT4EP INT3EP INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 99

... T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF ...

Page 100

... Interrupt request has not occurred DS39975A-page 100 R/W-0, HS R/W-0, HS R/W-0, HS T5IF T4IF OC4IF R/W-0, HS R/W-0, HS R/W-0, HS INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0, HS U-0 OC3IF — bit 8 R/W-0, HS R/W-0, HS MI2C1IF SI2C1IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 101

... OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS OC8IF OC7IF ...

Page 102

... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39975A-page 102  2010 Microchip Technology Inc. ...

Page 103

... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — — ...

Page 104

... Unimplemented: Read as ‘0’ DS39975A-page 104 U-0 U-0 U-0 — — — U-0 R/W-0, HS R/W-0, HS — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 R/W-0, HS — LVDIF bit 8 R/W-0, HS U-0 U1ERIF — bit Bit is unknown ...

Page 105

... U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS OC9IF SPI3IF ...

Page 106

... Unimplemented: Read as ‘0’ DS39975A-page 106 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 107

... Interrupt request is enabled 0 = Interrupt request is not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 (1) ...

Page 108

... SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. DS39975A-page 108 (1)  2010 Microchip Technology Inc. ...

Page 109

... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...

Page 110

... DS39975A-page 110 U-0 U-0 — — U-0 U-0 (1) — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 SI2C2IE — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 111

... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — — U-0 ...

Page 112

... Interrupt request not enabled DS39975A-page 112 R/W-0 R/W-0 R/W-0 OC9IE SPI3IE SPF3IE R/W-0 R/W-0 R/W-0 SI2C3IE U3TXIE U3RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U4TXIE U4RXIE bit 8 R/W-0 U-0 U3ERIE — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 113

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...

Page 114

... Unimplemented: Read as ‘0’ DS39975A-page 114 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 115

... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...

Page 116

... Interrupt source is disabled DS39975A-page 116 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 117

... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...

Page 118

... Interrupt source is disabled DS39975A-page 118 R/W-0 U-0 R/W-1 IC8IP0 — IC7IP2 U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP1 IC7IP0 bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 119

... OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 ...

Page 120

... Interrupt source is disabled DS39975A-page 120 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 121

... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 ...

Page 122

... Unimplemented: Read as ‘0’ DS39975A-page 122 R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC4IP1 IC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 123

... Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 ...

Page 124

... Interrupt source is disabled DS39975A-page 124 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 PMPIP0 — OC8IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 OC8IP1 OC8IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 125

... SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 ...

Page 126

... Unimplemented: Read as ‘0’ DS39975A-page 126 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 INT4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 127

... RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...

Page 128

... Unimplemented: Read as ‘0’ DS39975A-page 128 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 129

... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — — U-0 ...

Page 130

... Unimplemented: Read as ‘0’ DS39975A-page 130 R/W-0 U-0 R/W-1 U3TXIP0 — U3RXIP2 R/W-0 U-0 U-0 U3ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U3RXIP1 U3RXIP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 131

... Unimplemented: Read as ‘0’ bit 2-0 SI2C3IP<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 — USB1IP2 R/W-0 ...

Page 132

... Interrupt source is disabled DS39975A-page 132 R/W-0 U-0 R/W-1 SPI3IP0 — SPF3IP2 R/W-0 U-0 R/W-1 U4TXIP0 — U4RXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF3IP1 SPF3IP0 bit 8 R/W-0 R/W-0 U4RXIP1 U4RXIP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 133

... Unimplemented: Read as ‘0’ bit 2-0 OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — — R/W-0 ...

Page 134

... ILR3 ILR2 R-0, HSC R-0, HSC R-0, HSC VECNUM4 VECNUM3 VECNUM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0, HSC R-0, HSC ILR1 ILR0 bit 8 R-0, HSC R-0, HSC VECNUM1 VECNUM0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 135

... If the ISR is coded in assembly language, it must be termi- nated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 7.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, ...

Page 136

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 136  2010 Microchip Technology Inc. ...

Page 137

... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY • An on-chip PLL block to boost internal operating frequency on select internal and external oscillator sources, and to provide a precise clock source for peripherals, such as USB • Software controllable switching between various clock sources • ...

Page 138

... Oscillator Source POSCMD<1:0> Internal 11 Internal 11 Internal 11 Secondary 11 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 bits, FNOSC<2:0> (Configuration Configuration bits (Configuration FNOSC<2:0> Notes 1, 2 111 1 110 1 101 1 100 — 011 1 011 — 010 — 010 1 010 1 001 1 000  2010 Microchip Technology Inc. ...

Page 139

... IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...

Page 140

... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected. DS39975A-page 140 (2) (3)  2010 Microchip Technology Inc. ...

Page 141

... Reserved: Reserved bit; do not use bit 3-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...

Page 142

... DS39975A-page 142 U-0 U-0 — — R/W-0 R/W-0 (1) (1) (1) TUN4 TUN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 143

... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...

Page 144

... The 96 MHz PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output, using the PLLDIV<2:0> Config- uration bits (Configuration Word 2<14:12> in most devices).  2010 Microchip Technology Inc. ...

Page 145

... None (00) 2 (01) 4 (10) 8 (11) Note 1: These options are not compatible with USB operation. They may be used whenever the PLL branch is selected and the USB module is disabled.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY  MHz 96 MHz PLL 32 MHz  the system clock. Figure 8-2 shows this logic in the system clock sub-block ...

Page 146

... HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL ECPLL, HSPLL, XTPLL, FRCPLL ECPLL, HSPLL, XTPLL, FRCPLL PLL Division (PLLDIV<2:0>) 12 (111) 8 (110) 6 (101) 5 (100) 4 (011) 3 (010) 2 (001) 1 (000)  2010 Microchip Technology Inc. ...

Page 147

... They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is sleeping and waiting for a bus attachment).  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 8.6 Reference Clock Output In addition to the CLKO output (F ...

Page 148

... Sleep mode. DS39975A-page 148 R/W-0 R/W-0 R/W-0 (1) ROSEL RODIV3 RODIV2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 RODIV1 RODIV0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 149

... PWRSAV instruction is shown in Example 9-1. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “wake-up”.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 9.2.1 SLEEP MODE Sleep mode has these features: • ...

Page 150

... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows possible further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.  2010 Microchip Technology Inc. ...

Page 151

... CK WR PORT Data Latch Read LAT Read PORT  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY When a peripheral is enabled and it is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...

Page 152

... Make sure to disable the analog output function on 0 the pin if any is present. Tolerated Input V Only Tolerates input levels above V 5.5V for most standard logic. . Voltage excursions DD Comments Description input levels are tolerated. , useful DD  2010 Microchip Technology Inc. ...

Page 153

... Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ Note 1: This register is not available on 64-pin devices (PIC24FJXXXGB206).  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 R/W-1 — ...

Page 154

... ANSC4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 ANSB9 ANSB8 bit 8 R/W-1 R/W-1 ANSB1 ANSB0 bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 155

... Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 8-0 Unimplemented: Read as ‘0’ Note 1: This register is not available in 64-pin devices (PIC24FJXXXGB206).  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — ...

Page 156

... U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 R/W-1 — ANSF0 bit Bit is unknown R/W-1 R/W-1 ANSG9 ...

Page 157

... PORTB<15:8> as inputs and PORTB<7:0> as outputs Nop(); //Delay 1 cycle If (PORTBbits.RB13 //Next Instruction  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the CNPU1 through CNPU6 registers (for pull-ups), and the CNPD1 through CNPD6 registers (for pull-downs) ...

Page 158

... RPn/RPIn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the max- imum number of Peripheral Pin Selections supported by the device.  2010 Microchip Technology Inc. peripherals, ...

Page 159

... UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Function Name Register INT1 RPINR0 INT2 RPINR1 ...

Page 160

... Output Compare 8 U3TX UART3 Transmit (3) U3RTS UART3 Request To Send U4TX UART4 Transmit (3) U4RTS UART4 Request To Send SDO3 SPI3 Data Output SCK3OUT SPI3 Clock Output SS3OUT SPI3 Slave Select Output OC9 Output Compare 9 C3OUT Comparator 3 Output (unused)  2010 Microchip Technology Inc. Null NC ...

Page 161

... Total 64-Pin 28 (PIC24FJXXXGB206) 100/121-Pin 32 (PIC24FJXXXGB210)  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 10.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these reg- isters, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON< ...

Page 162

... OSCCON,#6"); ("MOV #OSCCON, w1 \n" "MOV #0x46, w2 \n" "MOV #0x57, w3 \n" "MOV.b w2, [w1]\ n" "MOV.b w3, [w1] \n" "BSET OSCCON, #6") ;  2010 Microchip Technology Inc. ...

Page 163

... INT3R<5:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Note: Input and output register values can only be changed if IOLOCK (OSCCON<6> ...

Page 164

... T2CKR4 T2CKR3 T2CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-1 R/W-1 INT4R1 INT4R0 bit Bit is unknown R/W-1 R/W-1 T3CKR1 T3CKR0 bit 8 R/W-1 R/W-1 T2CKR1 T2CKR0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 165

... IC2R<5:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 T5CKR4 ...

Page 166

... IC5R4 IC5R3 IC5R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC4R1 IC4R0 bit 8 R/W-1 R/W-1 IC3R1 IC3R0 bit Bit is unknown R/W-1 R/W-1 IC6R1 IC6R0 bit 8 R/W-1 R/W-1 IC5R1 IC5R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 167

... OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 ...

Page 168

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC9R1 IC9R0 bit 8 U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 U3RXR1 U3RXR0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 169

... U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 ...

Page 170

... SS1R4 SS1R3 SS1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 SCK1R1 SCK1R0 bit 8 R/W-1 R/W-1 SDI1R1 SDI1R0 bit Bit is unknown R/W-1 R/W-1 U3CTSR1 U3CTSR0 bit 8 R/W-1 R/W-1 SS1R1 SS1R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 171

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 ...

Page 172

... SDI3R4 SDI3R3 SDI3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 U4CTSR1 U4CTSR0 bit 8 R/W-1 R/W-1 U4RXR1 U4RXR0 bit Bit is unknown R/W-1 R/W-1 SCK3R1 SCK3R0 bit 8 R/W-1 R/W-1 SDI3R1 SDI3R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 173

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Slave Select Input (SS31IN) to the Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 — — ...

Page 174

... RP2R4 RP2R3 RP2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP1R1 RP1R0 bit 8 R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP3R1 RP3R0 bit 8 R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 175

... Peripheral output number n is assigned to pin, RP7 (see Table 10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see Table 10-4 for peripheral function numbers).  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 (1) (1) ...

Page 176

... RP10R4 RP10R3 RP10R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP9R1 RP9R0 bit 8 R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown R/W-0 R/W-0 RP11R1 RP11R0 bit 8 R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 177

... Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Table 10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 ...

Page 178

... RP18R4 RP18R3 RP18R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP17R1 RP17R0 bit 8 R/W-0 R/W-0 RP16R1 RP16R0 bit Bit is unknown R/W-0 R/W-0 RP19R1 RP19R0 bit 8 R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 179

... Peripheral output number n is assigned to pin, RP23 (see Table 10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see Table 10-4 for peripheral function numbers).  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 ...

Page 180

... RP26R4 RP26R3 RP26R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP25R1 RP25R0 bit 8 R/W-0 R/W-0 RP24R1 RP24R0 bit Bit is unknown R/W-0 R/W-0 RP27R1 RP27R0 bit 8 R/W-0 R/W-0 RP26R1 RP26R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 181

... Unimplemented: Read as ‘0’ bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Table 10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 RP29R4 ...

Page 182

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 182  2010 Microchip Technology Inc. ...

Page 183

... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...

Page 184

... DS39975A-page 184 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 185

... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...

Page 186

... The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39975A-page 186 Gate Sync PR3 PR2 (PR5) (PR4) Comparator MSB LSB TMR2 TMR3 (TMR5) (TMR4) 16 (1) ( TMR3HLD (TMR5HLD) TCKPS<1:0> TON 2 1x Prescaler 1, 8, 64, 256 01 00 (2) TGATE (2) TCS Sync  2010 Microchip Technology Inc. ...

Page 187

... Equal Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 2: The ADC event trigger is available only on Timer3.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 1x Gate Sync 01 ...

Page 188

... DS39975A-page 188 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 189

... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 (1) — ...

Page 190

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 190  2010 Microchip Technology Inc. ...

Page 191

... Trigger Trigger Sources Logic Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 13.1 General Operating Modes 13.1.1 SYNCHRONOUS AND TRIGGER ...

Page 192

... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (performed automatically by hardware).  2010 Microchip Technology Inc. for both modules configure ...

Page 193

... Input capture module is turned off Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 ICTSEL2 ...

Page 194

... R/W-0 R/W-1 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (1) (1) (1) (2) (2) (2) (2) (2) (2) (2) U-0 U-0 R/W-0 — — IC32 bit 8 R/W-1 R/W-0 R/W-1 SYNCSEL1 SYNCSEL0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 195

... Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...

Page 196

... Trigger mode operation starts after a trigger source event occurs. OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> (1) OCx Pin OC Output and Fault Logic (2) OCFA/OCFB OCx Interrupt the time base source with the  2010 Microchip Technology Inc. ...

Page 197

... Single Compare modes and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode registers ...

Page 198

... Reset Comparator Match Event OCxRS Buffer Rollover/Reset OCxRS (1) • (Timer Prescale Value Doze mode and PLL are disabled. OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> (1) OCx Pin OC Output and Fault Logic (2) OCFA/OCFB OCx Interrupt  2010 Microchip Technology Inc. ...

Page 199

... Based /2; Doze mode and PLL are disabled. CY OSC  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY • If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). • If OCxRS is greater than PRy, the pin will remain high (100% duty cycle) ...

Page 200

... OCTSEL0 R/W-0 R/W-0 (2) (2) OCFLT0 TRIGMODE OCM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) CY (2) (3) (2) (4) (2) (4) (2,4) (2,4) R/W-0 R/W-0 (2) (2) ENFLT2 ENFLT1 bit 8 R/W-0 R/W-0 (1) (1) (1) OCM1 OCM0 bit Bit is unknown (2,3)  2010 Microchip Technology Inc. ...

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