PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet
PIC18F45J10-I/ML
Specifications of PIC18F45J10-I/ML
Related parts for PIC18F45J10-I/ML
PIC18F45J10-I/ML Summary of contents
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... Microchip Technology Inc. PIC18F45J10 Family 28/40/44-Pin High-Performance, RISC Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS39682B ...
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... MCUs, K ® EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , microID, MPLAB, PIC, PICmicro, PICSTART code hopping devices, Serial ® © 2006 Microchip Technology Inc. ...
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... PIC18F44J10 16K 8192 PIC18F45J10 32K 16384 © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Peripheral Highlights: • High-current sink/source 25 mA/25 mA (PORTB and PORTC) • Three programmable external interrupts • Four input change interrupts • One Capture/Compare/PWM (CCP) module • One Enhanced Capture/Compare/PWM (ECCP) ...
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... PIC18F45J10 FAMILY Pin Diagrams 28-Pin SPDIP, SOIC, SSOP (300 MIL) MCLR RA0/AN0 RA1/AN1 RA2/AN2/V /CV REF - RA3/AN3/V V DDCORE RA5/AN4/SS1/C2OUT OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK1/SCL1 * Pin feature is dependent on device configuration. 28-Pin QFN RA2/AN2/V -/CV REF RA3/AN3/V V DDCORE RA5/AN4/SS1/C2OUT OSC1/CLKI OSC2/CLKO * Pin feature is dependent on device configuration. ...
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... RE1/WR/AN6 RE2/CS/AN7 OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK1/SCL1 RD0/PSP0/SCK2/SCL2 RD1/PSP1/SDI2/SDA2 * Pin feature is dependent on device configuration. 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D AV RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 * Pin feature is dependent on device configuration. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY VREF REF 5 36 CAP ...
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... PIC18F45J10 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2* * Pin feature is dependent on device configuration. DS39682B-page RC0/T1OSO/T1CKI 2 OSC2/CLKO OSC1/CLKI PIC18F44J10 PIC18F45J10 27 RE2/CS/AN7 7 26 RE1/WR/AN6 8 25 RE0/RD/AN5 9 24 RA5/AN4/SS1/C2OUT DDCORE Preliminary /V CAP © 2006 Microchip Technology Inc. ...
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... Appendix A: Revision History............................................................................................................................................................. 341 Appendix B: Migration Between High-End Device Families............................................................................................................... 341 The Microchip Web Site ..................................................................................................................................................................... 353 Customer Change Notification Service .............................................................................................................................................. 353 Customer Support .............................................................................................................................................................................. 353 Reader Response .............................................................................................................................................................................. 354 PIC18F45J10 family Product Identification System ........................................................................................................................... 355 © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682B-page 5 ...
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... PIC18F45J10 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Microchip Technology Inc. PIC18F45J10 FAMILY 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F45J10 family offer three different oscillator options. These include: • One Crystal mode, using crystals or ceramic resonators • One External Clock mode • INTRC source (approximately 31 kHz) ...
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... These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. The PIC18F45J10 family of devices provides an on-chip voltage regulator to supply the correct voltage levels to the core. Parts designated with an “F” part number (such as PIC18F25J10) have the voltage regulator enabled. ...
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... Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled Packages 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN Note 1: BOR is not available in PIC18LF2XJ10/4XJ10 devices. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY PIC18F25J10 DC – 40 MHz 16384 32768 8192 16384 768 1536 19 19 Ports ...
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... PIC18F45J10 FAMILY FIGURE 1-1: PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (16/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine Instruction Control Signals ...
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... Timer0 Comparator ECCP1 Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: BOR is not available in PIC18LF2XJ10/4XJ10 devices. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Data Bus<8> Data Latch 8 Data Memory (3.9 Kbytes) Address Latch PCL 12 Data Address< ...
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... PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, Pin Name SOIC, QFN SSOP MCLR 1 26 MCLR OSC1/CLKI 9 6 OSC1 CLKI OSC2/CLKO 10 7 OSC2 CLKO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 25 22 RB4 ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR 1 18 MCLR OSC1/CLKI 13 32 OSC1 CLKI OSC2/CLKO 14 33 OSC2 CLKO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/INT0/FLT0/AN12 33 9 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 34 10 RB1 INT1 AN10 RB2/INT2/AN8 35 11 RB2 INT2 AN8 RB3/AN9/CCP2 36 12 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 37 14 RB4 KBI0 ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/PSP0/SCK2 SCL2 RD0 PSP0 SCK2 SCL2 RD1/PSP1/SDI2/SDA2 20 39 RD1 PSP1 SDI2 SDA2 RD2/PSP2/SDO2 21 40 RD2 PSP2 SDO2 RD3/PSP3/SS2 22 41 RD3 PSP3 SS2 RD4/PSP4 27 2 RD4 ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 22 Preliminary © 2006 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F45J10 family of devices can be operated in five different oscillator modes High-Speed Crystal/Resonator 2. HSPLL High-Speed Crystal/Resonator with Software PLL Control 3. EC External Clock with F OSC 4. ECPLL External Clock with Software PLL Control 5. INTRC Internal 31 kHz Oscillator Four of these are selected by the user by programming the FOSC2:FOSC0 configuration bits ...
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... PIC18F45J10 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...
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... Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 2-4: HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC2 OSC1 Mode ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F45J10 family devices are shown in Figure 2-5. See Section 20.0 “Special Features of the CPU” for Configuration register details ...
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... FOSC2. 2.6.2 OSCILLATOR TRANSITIONS PIC18F45J10 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F45J10 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 IDLEN bit 7 bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as ‘0’ bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Oscillator Start-up Timer time-out has expired ...
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... Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 30 Preliminary © 2006 Microchip Technology Inc. ...
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... POWER-MANAGED MODES The PIC18F45J10 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F45J10 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... These intervals are not shown to scale. OST OSC © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-3) ...
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... PIC18F45J10 FAMILY 3.3 Sleep Mode The power-managed Sleep mode is identical to the leg- acy Sleep mode offered in all other PICmicro devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-4). All clock source status bits are cleared ...
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... Peripheral Clock Program Counter Wake Event © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS1:SCS0 to ‘ ...
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... PIC18F45J10 FAMILY 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP ...
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... RESET The PIC18F45J10 family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F45J10 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 IPEN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) ...
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... Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 4- Note 1: External Power-on Reset circuit is required ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F45J10 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE PWRT ...
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... PIC18F45J10 FAMILY 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F45J10 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F2XJ10 PIC18F4XJ10 POSTINC2 PIC18F2XJ10 PIC18F4XJ10 POSTDEC2 PIC18F2XJ10 PIC18F4XJ10 PREINC2 PIC18F2XJ10 PIC18F4XJ10 PLUSW2 PIC18F2XJ10 PIC18F4XJ10 FSR2H PIC18F2XJ10 PIC18F4XJ10 FSR2L PIC18F2XJ10 PIC18F4XJ10 STATUS PIC18F2XJ10 PIC18F4XJ10 TMR0H PIC18F2XJ10 PIC18F4XJ10 TMR0L ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F45J10 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices TRISE PIC18F2XJ10 PIC18F4XJ10 TRISD PIC18F2XJ10 PIC18F4XJ10 TRISC PIC18F2XJ10 PIC18F4XJ10 TRISB PIC18F2XJ10 PIC18F4XJ10 TRISA PIC18F2XJ10 PIC18F4XJ10 SSP2BUF PIC18F2XJ10 PIC18F4XJ10 LATE PIC18F2XJ10 PIC18F4XJ10 LATD PIC18F2XJ10 PIC18F4XJ10 LATC PIC18F2XJ10 PIC18F4XJ10 LATB ...
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... Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F45J10 FAMILY DEVICES CALL,RCALL,RETURN RETFIE,RETLW Program Memory PIC18FX4J10 © 2006 Microchip Technology Inc. ...
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... PIC18F45J10 FAMILY 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs ...
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... PIC18F45J10 FAMILY 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F45J10 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F45J10 family devices implement all 16 banks. Figure 5-5 shows the data memory organization for the PIC18F45J10 family devices ...
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... PIC18F45J10 FAMILY FIGURE 5-5: DATA MEMORY MAP FOR PIC18F24J10/44J10 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh = 0101 00h Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 ...
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... When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Data Memory 000h 7 00h ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F45J10 FAMILY DEVICES Address Name Address FFFh ...
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... See Section 4.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as individual unimplemented bits should be interpreted as ‘-’. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 4 Bit 3 Bit 2 Bit 1 Top-of-Stack Upper Byte (TOS<20:16>) Return Stack Pointer Holding Register for PC< ...
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... PIC18F45J10 FAMILY TABLE 5-2: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN — — WDTCON — — — RCON IPEN — — TMR1H ...
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... See Section 4.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as individual unimplemented bits should be interpreted as ‘-’. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 4 Bit 3 Bit 2 Bit 1 SYNC ...
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... PIC18F45J10 FAMILY 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruc- tion that affects the Z, DC bits, the results of the instruction are not written ...
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... Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘ ...
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... PIC18F45J10 FAMILY 5.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of reg- isters: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value ...
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... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM ...
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... PIC18F45J10 FAMILY FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) Example Instruction: ADDWF (Opcode: 0010 01da ffff ffff) When ‘a’ and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is inter- preted as a location in the Access RAM between 060h and 0FFh ...
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... F80h by using the BSR. FFFh © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 66 Preliminary © 2006 Microchip Technology Inc. ...
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... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F45J10 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... The WR bit can only be set (not cleared) in software Write cycle to the EEPROM is complete bit 0 Unimplemented: Read as ‘0’ Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-0 R/W-x — — FREE WRERR W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC18F45J10 FAMILY 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER ...
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... MOVFW TABLAT, W MOVF WORD_ODD © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F45J10 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
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... The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note: Unlike previous devices, the PIC18F45J10 family of devices does not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence. ...
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... PIC18F45J10 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 20.0 “ ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 76 Preliminary © 2006 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 7-2: ...
Page 80
... PIC18F45J10 FAMILY Example 7-3 shows the sequence unsigned multiplication. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 7- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ...
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... INTERRUPTS Members of the PIC18F45J10 family of devices have multiple interrupt sources and an interrupt priority fea- ture that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h ...
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... PIC18F45J10 FAMILY FIGURE 8-1: PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> PIR3<7:6> PIE3<7:6> IPR3<7:6> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> PIR3<7:6> PIE3<7:6> IPR3<7:6> DS39682B-page 80 TMR0IF ...
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... Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
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... PIC18F45J10 FAMILY REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 R/W-0 R/W-0 U-0 ...
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... PIC18F45J10 FAMILY 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module bus collision occurred (must be cleared in software bus collision occurred bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-0 U-0 — — BCL1IF — ...
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... PIC18F45J10 FAMILY 8.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
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... BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module Enabled 0 = Disabled bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-0 U-0 — — BCL1IE — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 90
... PIC18F45J10 FAMILY 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module High priority 0 = Low priority bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-1 U-0 — — BCL1IP — Writable bit U = Unimplemented bit, read as ‘ ...
Page 92
... PIC18F45J10 FAMILY 8.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 8-13: RCON: RESET CONTROL REGISTER R/W-0 IPEN bit 7 ...
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... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 92 Preliminary © 2006 Microchip Technology Inc. ...
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... EN RD Port Note 1: I/O pins have diode protection to V © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
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... PIC18F45J10 FAMILY 9.1.3 INTERFACING SYSTEM Though the V of the PIC18F45J10 family is 3.6V, DDMAX these devices are still capable of interfacing with 5V systems, even if the V of the target system is above IH 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 9-2), clearing the LAT bit for that ...
Page 97
... DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY I/O I/O Type ...
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... PIC18F45J10 FAMILY TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 PORTA — — LATA — — TRISA — — ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. ...
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... By programming the configuration bit, PBADEN, RB4:RB0 will alternatively be configured as digital inputs on POR. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Four of the PORTB pins (RB7:RB4) have an interrupt- on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt- on-change comparison) ...
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... PIC18F45J10 FAMILY TABLE 9-5: PORTB I/O SUMMARY TRIS Pin Function Setting RB0/INT0/FLT0/ RB0 0 AN12 1 INT0 1 FLT0 1 AN12 1 RB1/INT1/AN10 RB1 0 1 INT1 1 AN10 1 RB2/INT2/AN8 RB2 0 1 INT2 1 AN8 1 RB3/AN9/CCP2 RB3 0 1 AN9 1 (2) CCP2 0 1 RB4/KBI0/AN11 RB4 0 1 KBI0 1 AN11 1 RB5/KBI1/T0CKI/ RB5 ...
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... INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — ...
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... PIC18F45J10 FAMILY 9.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
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... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3. 2: Enhanced PWM output is available only on PIC18F44J10/45J10 devices. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY I/O I/O Type O DIG LATC< ...
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... PIC18F45J10 FAMILY TABLE 9-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register DS39682B-page 102 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 ...
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... Note Power-on Reset, these pins are configured as digital inputs. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 9.7 “Parallel Slave Port” ...
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... PIC18F45J10 FAMILY TABLE 9-9: PORTD I/O SUMMARY TRIS Pin Function I/O Setting RD0/PSP0/SCK2/ RD0 O 0 SCL2 I 1 PSP0 SCK2 SCL2 RD1/PSP1/SDI2/ RD1 O 0 SDA2 I 1 PSP1 SDI2 I 1 SDA2 RD2/PSP2/SDO2 RD2 PSP2 SDO2 O 0 RD3/PSP3/SS2 RD3 PSP3 SS2 I 1 RD4/PSP4 RD4 ...
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... IBF OBF CCP1CON P1M1 P1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — ...
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... PORTE, TRISE and LATE Registers Note: PORTE is only available in 40/44-pin devices. Depending on the particular PIC18F45J10 family device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. ...
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... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY R-0 R/W-0 R/W-0 U-0 OBF IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PIC18F45J10 FAMILY TABLE 9-11: PORTE I/O SUMMARY TRIS Pin Function Setting RE0/RD/AN5 RE0 AN5 1 RE1/WR/AN6 RE1 AN6 1 RE2/CS/AN7 RE2 AN7 1 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
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... PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY The timing for the control signals in Write and Read modes is shown in Figure 9-4 and Figure 9-5, respectively. ...
Page 112
... PIC18F45J10 FAMILY FIGURE 9-4: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF FIGURE 9-5: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 9-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 (1) PORTD RD7 RD6 (1) LATD PORTD Data Latch Register (Read and Write to Data Latch) ...
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... Prescale value Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1 ...
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... PIC18F45J10 FAMILY 10.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 10.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
Page 115
... T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 114 Preliminary © 2006 Microchip Technology Inc. ...
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... Stops Timer1 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 118
... PIC18F45J10 FAMILY 11.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 11-1: TIMER1 BLOCK DIAGRAM ...
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... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 120
... PIC18F45J10 FAMILY 11.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. ...
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... Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 120 Preliminary © 2006 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 124
... PIC18F45J10 FAMILY 12.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F45J10 family devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter ...
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... PIC18F45J10 FAMILY 13.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
Page 127
... CCP1CON<3:0> CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 13.2.3 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM3:CCPxM0). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared ...
Page 128
... PIC18F45J10 FAMILY 13.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
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... PIC18F45J10 FAMILY 13.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force ...
Page 131
... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 14.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY EQUATION 13-3: PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be cleared ...
Page 132
... PIC18F45J10 FAMILY TABLE 13-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — (1) PIR1 PSPIF ADIF (1) PIE1 PSPIE ADIE (1) IPR1 PSPIP ADIP TRISB PORTB Data Direction Control Register TRISC PORTC Data Direction Control Register TMR2 ...
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... Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY and restart. The Enhanced features are discussed in detail in Section 14.4 “Enhanced PWM Mode”. Capture, Compare and single output PWM functions of the ECCP module are the same as described for the standard CCP module ...
Page 134
... PIC18F45J10 FAMILY In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features. It is: • ECCP1DEL (Dead-Band Delay) 14.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
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... PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 14.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation ...
Page 136
... PIC18F45J10 FAMILY 14.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L register contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is ...
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... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 14.4.6 “Programmable Dead-Band Delay”). © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay 0 ...
Page 138
... PIC18F45J10 FAMILY 14.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 14-4). This mode can be used for half-bridge applications, as shown ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 140
... PIC18F45J10 FAMILY FIGURE 14-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F4XJ10 P1A P1B P1C P1D 14.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firm- ware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period t1 ...
Page 142
... PIC18F45J10 FAMILY 14.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power ...
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... Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 ( Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 144
... PIC18F45J10 FAMILY 14.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 14-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 145
... Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 14.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 146
... PIC18F45J10 FAMILY TABLE 14-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — (1) PIR1 PSPIF ADIF (1) PIE1 PSPIE ADIE (1) IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISB PORTB Data Direction Control Register ...
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... SSP1CON1 SSP2CON1 control the same features for two different modules. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 15.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
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... PIC18F45J10 FAMILY 15.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPxCON1) • MSSP Status Register (SSPxSTAT) • Serial Receive/Transmit Buffer Register (SSPxBUF) • MSSP Shift Register (SSPxSR) – Not directly accessible SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation ...
Page 149
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 OSC ...
Page 150
... PIC18F45J10 FAMILY 15.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCKx is the clock output) • Slave mode (SCKx is the clock input) • ...
Page 151
... Shift Register (SSPxSR) LSb MSb PROCESSOR 1 © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 15.3.4 TYPICAL CONNECTION Figure 15-2 shows a typical connection between two microcontrollers ...
Page 152
... PIC18F45J10 FAMILY 15.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 15-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be dis- abled (programmed as an input) ...
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... Flag SSPxSR to SSPxBUF © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
Page 154
... PIC18F45J10 FAMILY FIGURE 15-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF FIGURE 15-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 155
... EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 15.3.10 BUS MODE COMPATIBILITY Table 15-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
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... PIC18F45J10 FAMILY TABLE 15-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE (1) PIR1 PSPIF ADIF (1) PIE1 PSPIE ADIE (1) IPR1 PSPIP ADIP PIR3 SSP2IF BCL2IF PIE3 SSP2IE BCL2IE IPR3 SSP2IP BCL2IP TRISA — — TRISC TRISC7 TRISC6 ...
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... Stop bit Detect Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.1 REGISTERS The MSSP module has six registers for I These are: • ...
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... PIC18F45J10 FAMILY REGISTER 15-3: SSPxSTAT: MSSPx STATUS REGISTER (I R/W-0 R/W-0 SMP CKE bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz Slew rate control enabled for High-Speed mode (400 kHz) ...
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... C Slave mode, 10-bit address 2 0110 = I C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 2 C™ MODE) R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 ...
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... PIC18F45J10 FAMILY REGISTER 15-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) ...
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... I C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPxSR register ...
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... PIC18F45J10 FAMILY 15.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPxSTAT< ...
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... FIGURE 15-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682B-page 161 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39682B-page 162 Preliminary © 2006 Microchip Technology Inc. ...
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... FIGURE 15-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682B-page 163 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS39682B-page 164 Preliminary © 2006 Microchip Technology Inc. ...
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... CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode The 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear ...
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... PIC18F45J10 FAMILY 15.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sam- pled low. Therefore, the CKP bit will not assert the ...
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... FIGURE 15-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682B-page 167 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) DS39682B-page 168 Preliminary © 2006 Microchip Technology Inc. ...
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... BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) GCEN (SSPxCON2<7>) © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. ...
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... PIC18F45J10 FAMILY 15.4.6 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions ...
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... MHz I C operation. See Section 15.4.7 “Baud Rate” for more detail. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2<0>). ...
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... PIC18F45J10 FAMILY 15.4.7 BAUD RATE Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 15-17). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The ...
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... Value BRG Reload © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 15-18) ...
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... PIC18F45J10 FAMILY 2 15.4 MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (T the SDAx pin is driven low ...
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... SDAx RSEN bit set by hardware on falling edge of ninth clock, end of Xmit SCLx © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Note 1: If RSEN is programmed while any other event is in progress, it will not take effect bus collision during the Repeated Start 2 C logic condition occurs if: • ...
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... PIC18F45J10 FAMILY 2 15.4. MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next trans- mission ...
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... FIGURE 15-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682B-page 177 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS39682B-page 178 Preliminary © 2006 Microchip Technology Inc. ...
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... ACK SDAx Note one Baud Rate Generator period. BRG © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.13 STOP CONDITION TIMING A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a bit, ...
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... PIC18F45J10 FAMILY 15.4.14 SLEEP OPERATION 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 15.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... SDAx = 0, SCLx = 1. S SSPxIF © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 15-28). If, however, a ‘1’ is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to ‘ ...
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... PIC18F45J10 FAMILY FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF S ‘0’ ‘0’ SSPxIF FIGURE 15-28: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION Less than T SDAx pulled low by other master ...
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... BCLxIF. Release SDAx and SCLx. RSEN S SSPxIF © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 15-29). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from ...
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... PIC18F45J10 FAMILY 15.4.17.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. b) After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY 2 C™ OPERATION Bit 5 ...
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... PIC18F45J10 FAMILY NOTES: DS39682B-page 186 Preliminary © 2006 Microchip Technology Inc. ...
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... Synchronous – Slave (half duplex) with selectable clock polarity © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/ EUSART: • bit SPEN (RCSTA<7>) must be set (= 1) • ...
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... PIC18F45J10 FAMILY REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG Slave mode (clock from external source) bit 6 ...
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... No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC18F45J10 FAMILY REGISTER 16-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 ABDOVF RCIDL bit 7 bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit ...
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... Legend Don’t care value of SPBRGH:SPBRG register pair © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY tageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared) ...
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... PIC18F45J10 FAMILY EXAMPLE 16-1: CALCULATING BAUD RATE ERROR For a device with MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: OSC Desired Baud Rate = F /(64 ([SPBRGH:SPBRG] + 1)) OSC Solving for SPBRGH:SPBRG ((F /Desired Baud Rate)/64) – 1 OSC = ((16000000/9600)/64) – [25.042 Calculated Baud Rate ...
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... Microchip Technology Inc. PIC18F45J10 FAMILY SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (K) (decimal) — ...
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... PIC18F45J10 FAMILY TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) BAUD F = 40.000 MHz OSC RATE Actual SPBRG Actual (K) % Rate value Error (K) (decimal) 0.3 0.300 0.00 8332 1.2 1.200 0.02 2082 2.4 2.402 0.06 1040 9.6 9.615 0.16 259 19.2 19.231 0.16 129 19 ...
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... RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. ...
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... PIC18F45J10 FAMILY FIGURE 16-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h RX pin BRG Clock Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 16-2: ...
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... BRG16 SPBRGH SPBRG Baud Rate Generator © 2006 Microchip Technology Inc. PIC18F45J10 FAMILY Once the TXREG register transfers the data to the TSR register (occurs in one T and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1< ...
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... PIC18F45J10 FAMILY FIGURE 16-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 16-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG ...