PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet
PIC18F4431-I/P
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PIC18F4431-I/P Summary of contents
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... PIC18F2331/2431/4331/4431 High Performance PWM and A/D 2003 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, Preliminary DS39616B ...
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... The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary 2003 Microchip Technology Inc. L ® code hopping devices, Serial OQ ...
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... Instructions (bytes) PIC18F2331 8192 4096 PIC18F2431 16384 8192 PIC18F4331 8192 4096 PIC18F4431 16384 8192 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power-Managed Modes: • Run • Idle • Sleep • Idle mode currents down to 5.8 A typical • Sleep current down to 0.1 A typical • ...
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... Preliminary RB7/KBI3/PGD RB6/KBI2/PGC (1) RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA RB7/KBI3/PGD RB6/KBI2/PGC (2) RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RD7/PWM7 RD6/PWM6 (4) RD5/PWM4 (3) RD4/FLTA (1) RC7/RX/DT/SDO RC6/TX/CK/SS (1) (1) RC5/INT2/SCK /SCL (1) (1) RC4/INT1/SDI /SDA RD3/SCK/SCL RD2/SDI/SDA 2003 Microchip Technology Inc. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RC0/T1OSO/T1CKI 32 2 OSC2/CLKO/RA6 OSC1/CLKI/RA7 4 PIC18F4331 PIC18F4431 27 RE2/AN8 7 RE1/AN7 8 26 RE0/AN6 9 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB 11 Preliminary DS39616B-page 3 ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. DS39616B-page 4 OSC2/CLKO/RA6 OSC1/CLKI/RA7 PIC18F4331 PIC18F4431 RE2/AN8 27 7 RE1/AN7 26 8 RE0/AN6 9 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB 11 Preliminary SS DD 2003 Microchip Technology Inc. ...
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... Appendix E: Migration from Mid-range to Enhanced Devices ........................................................................................................... 381 Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................. 381 INDEX ................................................................................................................................................................................................ 383 On-Line Support................................................................................................................................................................................. 391 Systems Information and Upgrade Hot Line ...................................................................................................................................... 391 Reader Response .............................................................................................................................................................................. 392 PIC18F2331/2431/4331/4431 Product Identification System ............................................................................................................ 393 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Preliminary DS39616B-page 5 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. DS39616B-page 6 Preliminary 2003 Microchip Technology Inc. ...
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... This document contains device specific information for the following devices: • PIC18F2331 • PIC18F4331 • PIC18F2431 • PIC18F4431 This family offers the advantages of all PIC18 micro- controllers – namely, high computational performance at an economical price, with the addition of high endur- ance enhanced Flash program memory and a high- speed 10-bit A/D converter ...
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... Timer5 as the time base, a special event trigger to other modules, and an adjustable noise filter on each IC input. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from over 2 minutes, that is stable across operating voltage and temperature. Preliminary 2003 Microchip Technology Inc. ...
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... Yes Yes Yes Yes 75 Instructions 75 Instructions 28-pin SDIP 28-pin SDIP 28-pin SOIC 28-pin SOIC Preliminary program memory (8 Kbytes for devices, 16 Kbytes for PIC18F4331 PIC18F4431 DC – 40 MHz DC – 40 MHz 8192 16384 4096 8192 768 768 256 256 34 34 Ports Ports Channels) (8 Channels) ...
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... RA2/AN2/V -/CAP1/INDX REF RA3/AN3/V +/CAP2/QEA REF RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO 8 PORTE (1, 2) MCLR/V /RE3 PP HS 10-bit ADC PCPWM MFM 2003 Microchip Technology Inc. SS ...
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... RE3 is available only when MCLR is disabled. 2: RD4 is the alternate pin for FLTA. 3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL respectively. 4: RD5 is the alternate pin for PWM4. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Data Bus<8> Data Latch 8 8 Data RAM (768 bytes) ...
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... A/D Reference Voltage (High) input Input capture pin Quadrature Encoder Interface channel A input pin. 6 I/O TTL Digital I/O. I Analog Analog input Input capture pin Quadrature Encoder Interface channel B input pin. CMOS Preliminary Description = CMOS compatible input or output = Input = Power 2003 Microchip Technology Inc. ...
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... PGD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. 21 ...
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... USART Synchronous Data (see related TX/CK). O — SPI data out. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. CMOS Preliminary Description 2 C mode. = CMOS compatible input or output = Input = Power 2003 Microchip Technology Inc. ...
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... AN5 LVDIN Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input Master Clear (Reset) input. This pin is an active-low. ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2003 Microchip Technology Inc. ...
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... RC7 RX DT SDO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTC is a bidirectional I/O port. 34 I/O ST Digital I/O. O — Timer1 oscillator output. ...
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... I ST Fault interrupt input pin. 3 I/O ST Digital I/O. O TTL PWM output 4. 4 I/O ST Digital I/O. O TTL PWM output 6. 5 I/O ST Digital I/O. O TTL PWM output 7. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2 C mode. 2003 Microchip Technology Inc. ...
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... DD NC — 12, 13, 33, 34 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. I Analog Analog input 6. 26 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 20 Preliminary 2003 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of manufacturers’ specifications. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 2-1: ( Config- OSC (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Configuration Register 1H) OSC2 HS Mode Crystal OSC1 Osc of external Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 PLL BLOCK DIAGRAM HS Osc Enable PLL Enable Phase F IN Comparator F OUT Loop Filter 4 VCO SYSCLK 2003 Microchip Technology Inc. ...
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... CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R values and the operating temperature ...
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... There is no indication that the shift has occurred. Oper- ation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. /4, OSC Preliminary 8 clock cycles (approximately 2003 Microchip Technology Inc. ...
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... Maximum frequency • • 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • 100000 = Minimum frequency Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 R/W-0 — TUN5 TUN4 TUN3 • • ...
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... SLEEP instruction will be ignored recommended that the Timer1 oscil- lator be operating and stable before exe- cuting the SLEEP instruction very long delay may occur while the Timer1 oscillator starts. Preliminary 2003 Microchip Technology Inc. ...
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... Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 C4NFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for Other Modules OSCCON<6:4> 8 MHz 111 4 MHz 110 2 MHz ...
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... Section 3.1.2 “Entering Power-Managed Modes”. DS39616B-page 28 (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 OSTS IOFS W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... ECIO EC LP, XT, and HS Note: See Table 4-1 in the Section 4.0 “Reset”, for time-outs due to Sleep and MCLR Reset. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 30 Preliminary 2003 Microchip Technology Inc. ...
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... RC_IDLE 1 1x Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires deciding if the CPU clocked or not, and selecting a clock source. The IDLEN bit controls CPU clocking, while the SC1:SCS0 bits select a clock source ...
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... Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). Preliminary 2003 Microchip Technology Inc. is less than 3V specifications are violated. ...
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... Features of the CPU”). In either case, the OSTS bit is set when the primary clock provides the system clocks. The IDLEN and SCS bits are not affected by the wake-up. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 WDT time-out Peripherals are causes a ... ...
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... TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake Event Note 1024 OST OSC PLL DS39616B-page PLL ( OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. Preliminary 2003 Microchip Technology Inc. ...
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... Clock Program PC Counter Wake Event 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately required between the wake event and when code exe- cution starts. This is required to allow the CPU to become ready to execute instructions ...
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... T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run Clock Transition PLL ( Clock Transition OSTS bit Set Preliminary 2003 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the pri- mary clock provides the system clock. The IDLEN and SCS bits are not affected by the wake-up Clock Transition Preliminary 2003 Microchip Technology Inc. ...
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... INTRC OSC1 CPU Clock Peripheral Clock Program PC Counter 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled, and the IOFS bit will remain clear ...
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... On all exits from Low-power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). Preliminary 2003 Microchip Technology Inc. ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power- Clock Ready ...
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... INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made, and in some cases, how large a change is needed. Three examples follow, but other techniques may be used. Preliminary 2003 Microchip Technology Inc. ...
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... When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.6.3 EXAMPLE MODE ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 44 Preliminary 2003 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block, and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... D005) for BOR (parameter #35), the brown-out situ- DD for less than T . The chip will BOR rises above BOR ; it then will keep the chip in BOR (parameter PWRT while the Power-up BOR , the Power-up Timer will execute BOR 2003 Microchip Technology Inc. ...
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... Legend unchanged unknown unimplemented bit, read as ‘0’. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (2) Power-up and Brown-out ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2003 Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets ...
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... Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets ...
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... Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39616B-page 54 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary 2003 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 , V RISE > PWRT T OST T PWRT T ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 56 Preliminary 2003 Microchip Technology Inc. ...
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... The PIC18F2331 and PIC18F4331 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F2431 and PIC18F4431 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The Reset vector address is at 000000h and the interrupt vector addresses are at 000008h and 000018h ...
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... This is not the same as a Reset, as the contents of the SFRs are not affected. Return Address Stack 11111 11110 11101 STKPTR<4:0> TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 Preliminary 00010 2003 Microchip Technology Inc. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 — ...
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... The PC increments address sequential instructions in the program memory. The CALL, RCALL, instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. Preliminary 2003 Microchip Technology Inc. GOTO and program branch ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.6 Instruction Flow/Pipelining An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2003 Microchip Technology Inc. ...
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... Data is transferred to/from program memory, one byte at a time. The Table Read/Table Write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory ...
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... The BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. 2003 Microchip Technology Inc. ...
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... FC1h ADCON1 FE0h BSR FC0h ADCON2 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. ...
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... N/A 49, 71 N/A 49, 71 N/A 49, 71 N/A 49, 71 N/A 49, 71 49, 71 ---- 0000 49, 71 xxxx xxxx DC C 49, 73 ---x xxxx 49, 135 0000 0000 49, 135 xxxx xxxx T0PS1 T0PS0 49, 133 11-- 1111 2003 Microchip Technology Inc. ...
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... These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 ...
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... PTMOD0 52, 186 0000 0000 — 00-- ---- 52, 186 0000 0000 184 ---- 0000 184 2003 Microchip Technology Inc. ...
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... These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 ...
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... Registers” provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. Direct Addressing (3) From Opcode 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 Preliminary 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 2003 Microchip Technology Inc. ...
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... FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 If INDF0, INDF1 or INDF2 are read indirectly via a FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected ...
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... INDIRECT ADDRESSING 3 11 Location Select Note 1: For register file map detail, see Table 5-1. DS39616B-page 72 0h RAM Address FFFh 12 File Address = access of an indirect addressing register File FSR Indirect Addressing FSRnH:FSRnL 0000h Data (1) Memory 0FFFh Preliminary 2003 Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged) ...
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... Power-on Resets may be detected. U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2003 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The program memory space is 16-bits wide, while the data RAM space is 8-bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
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... See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Note: Interrupt flag bit EEIF, in the PIR2 register, is set when the write is complete. It must be cleared in software. Preliminary 2003 Microchip Technology Inc. Table Latch (8-bit) TABLAT ...
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... Initiates a memory read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Legend Readable bit W = Writable bit x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-x — FREE WRERR S = Settable only U = Unimplemented bit, read as ‘ ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> Preliminary TBLPTRL 0 2003 Microchip Technology Inc. ...
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... MOVFW TABLAT MOVWF WORD_EVEN TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... Execute a NOP. 9. Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; point to Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts Preliminary 2003 Microchip Technology Inc. ...
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... WREN bit to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written ...
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... FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment ; TBLPTR ; loop until buffers are full Preliminary 2003 Microchip Technology Inc. ...
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... PIE2 OSFIE — — Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 84 Preliminary 2003 Microchip Technology Inc. ...
Page 87
... Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, oper- ations will access the data EEPROM memory. When set, program memory is accessed. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory ...
Page 88
... R = Readable bit W = Writable bit x = Bit is unknown DS39616B-page 86 U-0 R/W-0 R/W-x — FREE WRERR WREN S = Settable only U = Unimplemented bit, read as ‘0’ Value at POR ‘1’ = Bit is set Preliminary R/W-0 R/S-0 R/S bit 0 ‘0’ = Bit is cleared 2003 Microchip Technology Inc. ...
Page 89
... BSF INTCON, GIE SLEEP BCF EECON1, WREN 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 90
... POR, BOR Resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 — — RD xx-0 x000 uu-0 u000 CCP2IP 1--1 -1-1 1--1 -1-1 CCP2IF 0--0 -0-0 0--0 -0-0 CCP2IE 0--0 -0-0 0--0 -0-0 2003 Microchip Technology Inc. ...
Page 91
... Example 8-2 shows the sequence signed multiply. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Making the multiplier execute in a single cycle gives the following advantages: • ...
Page 92
... ARG2H, W SUBWFB RES3 ; CONT_CODE : Preliminary SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; F ; Add cross ; products ARG1H * ARG2L -> ; PRODH:PRODL ; F ; Add cross ; products ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2003 Microchip Technology Inc. ...
Page 93
... Individual interrupts can be disabled through their corresponding enable bits. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- ...
Page 94
... INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary 2003 Microchip Technology Inc. Wake- Power-Managed mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL\PEIE ...
Page 95
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...
Page 96
... DS39616B-page 94 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 97
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 — ...
Page 98
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2003 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 99
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Not used in PWM mode Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-0 U-0 — — EEIF — ...
Page 100
... R = Readable bit -n = Value at POR DS39616B-page 98 U-0 R/W-0 R/W-0 R/W-0 — PTIF IC3DRIF IC2QEIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary 2003 Microchip Technology Inc. R/W-0 R/W-0 IC1IF TMR5IF bit bit is unknown ...
Page 101
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 ADIE RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 102
... Value at POR DS39616B-page 100 U-0 U-0 R/W-0 U-0 — — EEIE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 U-0 R/W-0 LVDIE — CCP2IE bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 103
... IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 — PTIE IC3DRIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 104
... Value at POR DS39616B-page 102 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 105
... High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-1 U-0 — — EEIP — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 106
... Value at POR DS39616B-page 104 U-0 U-0 R/W-1 R/W-1 — — PTIP IC3DRIP IC2QEIP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary R/W-1 R/W-1 R/W-1 IC1IP TMR5IP bit bit is unknown 2003 Microchip Technology Inc. ...
Page 107
... POR: Power-on Reset Status bit For details of bit operation, see Register 5-3 bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-1 R-1 — — ...
Page 108
... Example 9-1 saves and restores the WREG, Status and BSR registers during an interrupt service routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 0000h) 2003 Microchip Technology Inc. ...
Page 109
... PORT Note 1: I/O pins have diode protection to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.1 PORTA, TRISA and LATA Registers PORTA is a 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 110
... Data Latch D N I/O Pin WR TRISA TRIS Latch V SS TTL Input Buffer RD PORTA To A/D Converter Preliminary BLOCK DIAGRAM OF RA1 LATA Q RA1 Analog Input Mode RD TRISA TTL I/O Pin Analog Input Mode Schmitt TTL Trigger Input Buffer 2003 Microchip Technology Inc. ...
Page 111
... FIGURE 10-5: BLOCK DIAGRAM OF RA4 Data Bus WR LATA or PORTA WR TRISA Note 1: Open-drain usually available on RA4 has been removed for this device. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RD LATA Data Latch Analog TRIS Latch Input Mode RD TRISA PORTA To A/D Converter To CAP3/QEB Preliminary ...
Page 112
... Bus WR LATA or I/O PORTA Pin SS TTL Input Buffer RD PORTA SCILLATOR I/O Pin V SS TTL Input Buffer D EN Preliminary BLOCK DIAGRAM OF RA7 SCILLATOR RD LATA Data Latch N I Pin INTOSC TRIS Latch w/RA7 Enable TTL Input RD TRISA Buffer 2003 Microchip Technology Inc. ...
Page 113
... RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: ANS5 through ANS8 are available only on the PIC18F4X31 devices. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Buffer TTL Input/output or analog input. ...
Page 114
... RB<0:3> and RB4 pins are multiplexed with the 14-bit PWM module for PWM<0:3> and PWM5 output. The RB5 pin can be configured by the configuration bit PWM4MX as the alternate pin for PWM4 output. Preliminary 2003 Microchip Technology Inc. ...
Page 115
... PORT/PWM Select PWM0,1,2, 3 Data Data Bus D WR LATB CK or PORTB Data Latch D WR TRISB CK TRIS Latch RD PORTB Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LATC TRISB Preliminary ...
Page 116
... Set RBIF From other RB7:RB4 pins Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39616B-page 114 LATC PORTB EN Q3 Preliminary V DD Weak P Pull- RB4 Pin N SS TTL Input Buffer Q1 2003 Microchip Technology Inc. ...
Page 117
... PORT/PWM Select PWM4 Data Data Bus PORT Q CK Data Latch TRIS CK TRIS Latch RD TRIS RD PORT Set RBIF From other RB7:RB4 pins LVP Configuration Bit 1 = Low V Prog Enable 0 = only HV Prog 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RBPU TTL Input Buffer Port EN Q3 ...
Page 118
... Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2: PGC is available on RB6. 3: PGD is available on RB7. DS39616B-page 116 Weak P Pull- Enable Debug BRBx 0 1 Enable Debug BTRISx TTL Input Buffer PORTB EN Q3 Preliminary RB7/RB6 Pin Schmitt Trigger 2003 Microchip Technology Inc. ...
Page 119
... INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP — Legend unknown unchanged value depends on condition. Shaded cells are not used by PORTB. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Function (1) Input/output pin, or PCPWM output PWM0. Internal software programmable weak pull-up. (1) Input/output pin, or PCPWM output PWM1. Internal software programmable weak pull-up ...
Page 120
... CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs Schmitt Trigger Preliminary 2003 Microchip Technology Inc. RC0 Pin Timer1 Oscillator To RC1 Pin ...
Page 121
... Note 1: FLTA input is multiplexed with RC1 and RD4 using FLTAMX configuration bit in CONFIG3L register. FIGURE 10-15: BLOCK DIAGRAM OF RC2 PORT/CCP1 Select CCP1 Data Out Data Bus D WR LATC CK or PORTC Data Latch D WR TRISC CK TRIS Latch RD TRISC RD PORTC CCP1 Input/FLTB input 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LATC LATC Q Q ...
Page 122
... TRIS Latch RD TRISC SDA Drive RD PORTC SDI/SDA Input Note 1: The SDI/SDA bits are multiplexed on RD2 and RC4 pins by SSPMX bit in the configuration register. DS39616B-page 120 Schmitt Trigger Preliminary RC3 Pin (1) EXCLKMX_enable DD RC4 Pin (1) SSPMX Schmitt Trigger 2003 Microchip Technology Inc. ...
Page 123
... Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the configuration register. FIGURE 10-19: BLOCK DIAGRAM OF RC6 USART Select TX Data Out/CK Data Bus D WR LATC CK or PORTC Data Latch D WR TRISC CK TRIS Latch RD TRISC USART Select RD PORTC CK Input SS input 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger LATC ...
Page 124
... RD TRISC (1) USART Select RD PORTC RX/DT Data Input Note 1: USART is in Synchronous Master Transmission mode only (SYNC = 2: SDO must have its TRISC bit cleared in order to be able to drive RC7. DS39616B-page 122 Schmitt Trigger TXEN = Preliminary RC7 Pin 1 ). 2003 Microchip Technology Inc. ...
Page 125
... INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP — Legend unknown unchanged 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin, Timer1 oscillator input, or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is disabled, or FLTA input. ...
Page 126
... MOVWF TRISD LATD Preliminary INITIALIZING PORTD ; Initialize PORTD by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs RD[7:6] Pin N SS Schmitt Trigger 2003 Microchip Technology Inc. ...
Page 127
... CK TRIS Latch RD TRISD RD PORTD FIGURE 10-23: BLOCK DIAGRAM OF RD4 RD LATD Data Bus LATD PORTD Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD FLTA input Note 1: FLTAMX is located in the configuration register. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LATD Schmitt Trigger Preliminary V DD ...
Page 128
... CK Q TRIS Latch RD TRISC SDA Drive RD PORTC SDI/SDA Input Note 1: The SDI/SDA bits are multiplexed on RD2 and RC4 pins by SSPMX bit in the configuration register. DS39616B-page 126 Schmitt Trigger Schmitt Trigger Preliminary 2003 Microchip Technology Inc. RD3 Pin (1) SSPMX RD2Pin (1) SSPMX ...
Page 129
... Note 1: The SDO output is multiplexed by SSPMX bit in the configuration register. FIGURE 10-27: BLOCK DIAGRAM OF RD0 RD LATD Data Bus LATD PORTD Data Latch TRISD Q CK TRIS Latch RD TRISD RD PORTD T0CKI/T5CKI Input Note 1: T0CKI/T5CKI are multiplexed by SSPMX bit in the configuration register. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger Schmitt Trigger ...
Page 130
... Input/output port pin, or PCPWM output PWM7. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD4 RD3 RD2 RD1 Preliminary Value on Value on all other POR, BOR Resets RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2003 Microchip Technology Inc. ...
Page 131
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE con- ...
Page 132
... Trigger RD LATE Latch PORTE High Voltage Detect MCLRE Internal MCLR FILTER Note 1: Pin requires special protection due to HV. DS39616B-page 130 RD LATE Analog Input Mode /RE3 PP HV Low Level MCLR Detect Preliminary RE<0:2> Pins Schmitt TTL Trigger 2003 Microchip Technology Inc. ...
Page 133
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 134
... PORTE Data Direction bits ANS4 ANS3 ANS2 ANS1 ANS12 ANS11 ANS10 ANS9 Preliminary Value on Value on Bit 0 all other POR, BOR Resets RE0 ---- q000 ---- q000 ---- -xxx ---- -uuu ---- -111 ---- -111 ANS0 1111 1111 1111 1111 ANS8 ---- ---0 ---- ---0 2003 Microchip Technology Inc. ...
Page 135
... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 136
... T0PS2, T0PS1, T0PS0 0 Sync with Internal TMR0L Clocks delay PSA Preliminary Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2003 Microchip Technology Inc. ...
Page 137
... PORTA Data Direction Register Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the Oscillator mode selected in Configuration Word 1H. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.2.1 SWITCHING PRESCALER ...
Page 138
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 136 Preliminary 2003 Microchip Technology Inc. ...
Page 139
... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Register 12-1 details the Timer1 control register. This register controls the Operating mode of the Timer1 module, and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON< ...
Page 140
... CCP Special Event Trigger CLR TMR1L TMR1ON on/off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Preliminary become inputs. That is, the Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Peripheral Clocks 2003 Microchip Technology Inc. ...
Page 141
... Capacitor values are for design guidance only. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode ...
Page 142
... For this method to be accurate, Timer1 must operate in Asynchronous mode, and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the rou- tine RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary 2003 Microchip Technology Inc. ...
Page 143
... T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 144
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 142 Preliminary 2003 Microchip Technology Inc. ...
Page 145
... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset ...
Page 146
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 TMR1IP -111 1111 -111 1111 0000 0000 0000 0000 1111 1111 1111 1111 2003 Microchip Technology Inc. ...
Page 147
... Note 1: For Timer5 to operate during Sleep mode, T5SYNC must be set. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is a general-purpose timer/counter that incorpo- rates additional features for use with the Motion Feed- back module (see Section 16.0 “Motion Feedback Module” ...
Page 148
... T5SYNC bit. The input on T5CKI is sampled on every Q2 and Q4 of the internal clock. The low to rise transition is decoded on three adjacent samples and Preliminary Internal Data Bus 1 0 Timer5 On/Off Write TMR5L Read TMR5L 8 8 2003 Microchip Technology Inc. ...
Page 149
... Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the actual high byte of the Timer5 register pair is not directly readable or writable, it must be read and written to through the Timer5 High Byte Buffer register (TMR5H) ...
Page 150
... TMR5CS • T5SYNC 14.8.1 INTERRUPT DETECT IN SLEEP MODE When configured as described above, Timer5 will continue to increment on each rising edge on T5CKI while in Sleep mode. When a TMR5/PR5 match occurs, an interrupt is generated which can wake the part. Preliminary 2003 Microchip Technology Inc. ...
Page 151
... Timer5 Period Register Low Byte T5CON T5SEN RESEN T5MOD CAP1CON — CAP1REN — DFLTCON — FLT4EN FLT3EN Legend unknown unchanged, – = unimplemented. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF PTIP IC3DRIP IC2QEIP IC1IP PTIE IC3DRIE IC2QEIE ...
Page 152
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 150 Preliminary 2003 Microchip Technology Inc. ...
Page 153
... Generate software interrupt-on-compare match (CCPxIF bit is set, CCP pin is unaffected) 1011 =Compare mode, Trigger special event (CCP2IF bit is set) 11xx =PWM mode Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 R/W-0 — ...
Page 154
... PWM Timer2 DS39616B-page 152 15.2 CCP2 Module (CCPR1) is Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. Preliminary 2003 Microchip Technology Inc. ...
Page 155
... Q’s Prescaler CCP2 pin and Edge Detect Q’s 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...
Page 156
... Special Event Trigger Set Flag bit CCP1IF S Output Logic Match R CCP1CON<3:0> Mode Select Special Event Trigger Set Flag bit CCP2IF S Output Logic Match R CCP2CON<3:0> Mode Select Preliminary CCPR1H CCPR1L Comparator TMR1H TMR1L Comparator CCPR2H CCPR2L 2003 Microchip Technology Inc. ...
Page 157
... PIE2 OSCFIE CMIE — IPR2 OSCFIP CMIP — Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF TXIF SSPIF ...
Page 158
... CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. Preliminary • OSC (TMR2 prescale value) Tosc • (TMR2 prescale value) 2003 Microchip Technology Inc. ...
Page 159
... DC2B1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.5.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
Page 160
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 158 Preliminary 2003 Microchip Technology Inc. ...
Page 161
... Counter overflow flag for low rotation speed • Utilizes Input Capture 1 logic (IC1) • High and low velocity support 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses ...
Page 162
... QEB Velocity Event Timer reset Direction QEA Position Counter Clock QEI Control CHGIF Logic INDX QEI Logic IC3DRIF QEI Mode Decoder IC2QEIF Preliminary TMR5IF Special Event output TMR5<15:0> 8 IC3IF 8 IC2IF 8 IC1IF Special Reset Trigger QEIF 8 8 2003 Microchip Technology Inc. ...
Page 163
... Q Clocks Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active. 2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Input channel (IC1) includes a special event trigger that can be configured for use in Velocity Measure- ment mode ...
Page 164
... CAP3BUF is enabled as MAXCNT when QEI mode is active. DS39616B-page 162 and Mode Select Q’s (1) (1) ICxIF Capture Clock/ (1) CAPxBUF_clk Reset/ Interrupt Decode Logic Reset (1) Q clocks CAPxM<3:0> Preliminary Capture Clock (1,2,3) CAPxBUF TMR5 Enable TMR5 TMR5 Reset Timer Reset Control (2) CAPxREN 2003 Microchip Technology Inc. ...
Page 165
... For example, ‘CAPxREN’ may refer to the Capture Reset Enable bit in CAP1CON, CAP2CON or CAP3CON. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Registers U-0 R/W-0 R/W-0 — ...
Page 166
... ABCD 0016 BCF CAP1CON, CAP1REN . In the event that a write to TMR5 coincides with an input capture event, CY clock edge when the capture event takes place (see Note 4 CY Preliminary 0002 0000 0001 0003 0002 Note 5 2003 Microchip Technology Inc. ...
Page 167
... Pulse Width Measurement mode active on each rising edge detected. In the falling to rising Pulse Width Measure- ment mode active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. CAP1REN bit has no bearing in this mode. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 of the CAPx input pin (CAPxM3:CAPxM0 = 0110 the rising to falling edge (CAPxM3:CAPxM0 = 0111) ...
Page 168
... Any change on CAP1, CAP2 or CAP3 is detected and the associated time base count is captured. For position and velocity measurement in this mode, the timer can be optionally reset (see Section 16.1.6 “Timer5 Reset” for Reset options Preliminary 2003 Microchip Technology Inc. ...
Page 169
... POR or BOR. f) The timer value is not affected when switch- ing into and out of various input capture modes. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1.6 TIMER5 RESET Every Input Capture trigger can optionally reset (TMR5). Capture Reset Enable bit, CAPxREN, gates the automatic Reset of the time base of the capture event with this enable Reset signal ...
Page 170
... Section 16.2.6 “Velocity Measurement”. While in QEI mode, the CAP2BUF and CAP3BUF reg- isters of channel IC2 and IC3 are used for position determination. They are remapped as the POSCNT and MAXCNT buffer registers, respectively. Preliminary 0000 0001 2003 Microchip Technology Inc. ...
Page 171
... Measurement Input Capture on State 1000 Change Note 1: Timer5 may be reset on capture events only when CAPxRE = 1. 2: Trigger mode will not reset Timer5 unless RESEN = 0 in the T5CON register. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Reset Timer Timer on Capture (1) TMR5 optional Simple edge Capture mode (includes a ...
Page 172
... Figure 16-8. QEI Module Direction change Set CHGIF Timer reset Velocity Event Postscaler QEB Direction POSCNT/CAP2BUF Clock QEA INDX Comparator MAXCNT/CAP3BUF QEI Control Logic Position Counter Preliminary Reset Timer5 Velocity Capture 8 Set UP/DOWN 8 Reset on match Set IC2QEIF 2003 Microchip Technology Inc. ...
Page 173
... VREGL, POSCNTH, POSCNTL, MAXCNTH, and MAXCNTL registers (respectively) for the QEI. 4: ERROR bit must be cleared in software. Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The operation of the QEI is controlled by the QEICON configuration register. See Register 16-2. Note: In the event that both QEI and IC are enabled, QEI will take precedence and IC will remain disabled ...
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... Rising Detected QEA QEB QEA QEB QEA rising QEA falling QEB rising x QEB falling x Note 1: When UP/DOWN = 1, the position counter is incremented; when UP/DOWN = 0, the position counter is decremented. Preliminary 2003 Microchip Technology Inc. Detected Pos. (1) Falling Cntrl. x INC x DEC x DEC x INC ...
Page 175
... T the load operation (see Figure 16-10). The value of the position counter is not affected during QEI mode changes, nor when the QEI is disabled altogether. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.4 QEI INTERRUPTS The position counter interrupt occurs, and the interrupt flag (IC2QEIF) is set, based on the following events: • ...
Page 176
... Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. DS39616B-page 174 CY ( 16T QEI = F QEI CY Forward Reverse - Note 6 Note 2 (3) ( (4) ( (5) Q1 Preliminary /16. clock by the input CY 2003 Microchip Technology Inc. ...
Page 177
... To optimize register space, the input capture channel one (IC1) is used to capture TMR5 counter values. Input capture buffer register, CAP1BUF, is redefined in Velocity Measurement mode, VELM = 0, as the Velocity Register buffer (VREGH, VREGL). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Forward Reverse Note 2 Note 2 ...
Page 178
... TMR5 is reset upon a capture event. Figure 16-13 shows the velocity measurement timing diagram. TMR5 Reset Reset Logic Velocity Capture Postscaler Direction Position Counter Clock Preliminary Clock TMR5 Velocity Mode IC1 (VELR Register) 2003 Microchip Technology Inc. ...
Page 179
... The velocity event reduction ratio can be set with the PDEC1:PDEC0 control bits (QEICON<1:0>) to 1:4, 1:16, 1: reduction (1:1). The velocity postscaler settings are automatically reloaded from their previous values as the Velocity mode is re-enabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (1) Forward 1537 Old Value ...
Page 180
... Figure 16-14. R/W-0 R/W-0 R/W-0 R/W-0 FLT3EN FLT2EN FLT1EN FLTCK2 (1) (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary R/W-0 R/W-0 FLTCK1 FLTCK0 bit bit is unknown 2003 Microchip Technology Inc. ...
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... IC1 capture Velocity register event IC2QEIF IC2 capture Position measurement event IC3DRIF IC3 capture Direction change event 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (3) Noise glitch . CY 16.5 Operation in Sleep Mode 16.5.1 3X INPUT CAPTURE IN SLEEP MODE Since the input capture can operate only when its time base is configured in a Synchronous mode, the input capture will not capture any events ...
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... CAP1M1 CAP1M0 -0-- 0000 -0-- 0000 CAP2M1 CAP2M0 -0-- 0000 -0-- 0000 CAP3M1 CAP3M0 -0-- 0000 -0-- 0000 FLTCK1 FLTCK0 -000 0000 -000 0000 PDEC1 PDEC0 0000 0000 0000 0000 2003 Microchip Technology Inc. ...
Page 183
... Switched Reluctance Motors • Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The PWM module has the following features: • eight PWM I/O pins with four duty cycle generators. Pins can be paired to get a complete half-bridge control ...
Page 184
... Dead Time Generator and Override Logic PWM Generator Channel 0 #0 Dead Time Generator and Override Logic Special Event Postscaler Preliminary (2) PWM7 (2) (2) PWM6 PWM5 Output PWM4 Driver Block PWM3 PWM2 PWM1 PWM0 FLTA (2) FLTB Special Event Trigger 2003 Microchip Technology Inc. ...
Page 185
... In complimentary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3, and so on. The dead time 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 V DD Dead-Band ...
Page 186
... The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. Note: The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software. Preliminary 2003 Microchip Technology Inc. ...
Page 187
... The up/down counting modes produce center-aligned PWM generation. The Single-shot mode allows the PWM module to support pulse control of certain electronically commutated motors (ECMs) and produces edge-aligned operation. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PTMR Clock Timer RESET Up/Down Zero match ...
Page 188
... U-0 U-0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’= bit is set ‘0’ = bit is cleared Preliminary R/W-0 R/W-0 PTMOD0 bit bit is unknown U-0 U-0 U-0 — — — bit bit is unknown 2003 Microchip Technology Inc. ...
Page 189
... PIC18F2X31 devices; PWM[7:0] outputs are enabled for PIC18F4X31devices. When PWMEN2:PWMEN0 = 111, PWM outputs 1, 3 and 5 are enabled in PIC18F2X31devices; PWM outputs and 7 are enabled in PIC18F4X31 devices. 3: Unimplemented in PIC18F2X31 devices; maintain these bits clear. Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (1) (1) (1) R/W-1 R/W-1 R/W-0 ...
Page 190
... The PWM module must be capable of gener- ating PWM signals at the line frequency ( Hz) for certain power control applications. Preliminary U-0 R/W-0 R/W-0 — UDIS OSYNC bit bit is unknown /4) has prescaler OSC operating frequency of 40 MHz 2003 Microchip Technology Inc. ...
Page 191
... PTMR FFEh PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.4 PWM Time Base Interrupts The PWM timer can generate interrupts based on the modes of operation selected by PTMOD<1:0> bits and the postscaler bits (PTOPS< ...
Page 192
... The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. Figure 17-7 shows the interrupts in continuous Up/Down Counting mode FFFh 000h FFFh 000h 1 Preliminary 000h 000h 000h 000h 2003 Microchip Technology Inc. ...
Page 193
... PWM TIME BASE INTERRUPTS, UP/DOWN COUNTING MODE PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit PRESCALER = 1 PTMR 002h PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit PTIF is sampled here (every Q1). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 001h 000h 001h 000h 1 1 Preliminary Q2 Q3 ...
Page 194
... Do not change PTMOD while PTEN is active. It will yield unexpected results. To change PWM Timer mode of operation, first clear PTEN bit, load PTMOD with required data and then set PTEN 3FEh 3FFh 001h 000h 1 1 Preliminary 3FEh 3FDh 001h 002h 2003 Microchip Technology Inc. ...
Page 195
... Fosc/(PTMRPS/4) The PWM frequency is the inverse of period PWM frequency = ------------------------------ - PWM period 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 17-3: Resolution = The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 17-2 ...
Page 196
... PWM PERIOD BUFFER UPDATES IN UP/DOWN COUNTING MODES New PTPER value = 007 Old PTPER value = 004 DS39616B-page 194 Period value loaded from PTPER Buffer register New value written to PTPER buffer. Period value loaded from PTPER Buffer register New value written to PTPER buffer. Preliminary 2003 Microchip Technology Inc. ...
Page 197
... duty cycle match occurs duty cycle match occurs duty cycle match occurs on Q4 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCn hold the actual duty cycle value from PTMRH/L< ...
Page 198
... PTPER register. FIGURE 17-12: PTPER PTMR PDC Value (old) PDC (new) 0 Duty Cycle Active at beginning of period Duty cycle value loaded from buffer register New value written to duty cycle buffer Preliminary EDGE-ALIGNED PWM New Duty Cycle Latched Period 2003 Microchip Technology Inc. ...
Page 199
... Start of Duty Cycle first PWM Period 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Duty cycle value loaded from buffer register New values written to duty cycle buffer. inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
Page 200
... I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device resets. are the Preliminary TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS 3 Phase Load 2003 Microchip Technology Inc. ...