PIC16F684-I/ML Microchip Technology Inc., PIC16F684-I/ML Datasheet - Page 11

• Manufacturer Part Number: PIC16F684-I/ML
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 12 I/O, QFN-16
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F684-I/ML

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 16-pin QFN
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
© 2007 Microchip Technology Inc.
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note
Addr
1:
2:
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
WDTCON
CMCON0
CMCON1
ADRESH
ADCON0
Name
—
—
—
—
—
—
—
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
Port pins with analog functions controlled by the ANSEL register will read ‘0’ immediately after a Reset even though the data latches are
either undefined (POR) or unchanged (other Resets).
(2)
(2)
PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
Unimplemented
Unimplemented
Unimplemented
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ECCPASE
T1GINV
PRSEN
C2OUT
ADFM
IRP
P1M1
EEIF
Bit 7
GIE
—
—
—
—
—
—
(1)
TOUTPS3
ECCPAS2
TMR1GE
C1OUT
RP1
PDC6
VCFG
P1M0
Bit 6
PEIE
ADIF
—
—
—
—
—
(1)
TOUTPS2
ECCPAS1
T1CKPS1
CCP1IF
DC1B1
C2INV
PDC5
Bit 5
T0IE
RP0
RA5
RC5
—
—
—
—
TOUTPS1
ECCPAS0
T1CKPS0
WDTPS3
DC1B0
C1INV
PDC4
CHS2
INTE
Bit 4
C2IF
RA4
RC4
TO
—
Write Buffer for upper 5 bits of Program Counter
T1OSCEN
TOUTPS0
WDTPS2
CCP1M3
PSSAC1
PDC3
CHS1
RAIE
Bit 3
C1IF
RC3
RA3
CIS
PD
—
TMR2ON
WDTPS1
CCP1M2
T1SYNC
PSSAC0
OSFIF
PDC2
CHS0
Bit 2
T0IF
CM2
RA2
RC2
—
Z
GO/DONE
T2CKPS1
TMR1CS
CCP1M1
WDTPS0
PSSBD1
TMR2IF
T1GSS
PDC1
Bit 1
INTF
RC1
CM1
RA1
DC
T2CKPS0 -000 0000
SWDTEN
TMR1ON
CCP1M0
PSSBD0
C2SYNC
TMR1IF
PIC16F684
ADON
PDC0
RAIF
Bit 0
CM0
RA0
RC0
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--x0 x000
--xx 0000
---0 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
XXXX XXXX
XXXX XXXX
0000 0000
0000 0000
0000 0000
---0 1000 111, 104
0000 0000
---- --10
xxxx xxxx
00-0 0000
POR, BOR
Value on
DS41202F-page 9
—
—
—
—
—
—
—
19, 104
43, 104
19, 104
13, 104
19, 104
31, 104
40, 104
19, 104
15, 104
17, 104
47, 104
47, 104
50, 104
53, 104
54, 104
80, 104
80, 104
79, 104
96, 104
93, 104
61, 104
62, 104
71, 104
70, 104
Page
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—
—
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