PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet
PIC16F872-I/SP
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PIC16F872-I/SP Summary of contents
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... Microchip Technology Inc. 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D PIC16F872 Data Sheet DS30221C ...
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... Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. L ® code hopping devices, Serial EE OQ © 2006 Microchip Technology Inc. ...
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... Fully static design • Commercial, Industrial and Extended temperature ranges • Low power consumption: - < typical @ 5V, 4 MHz - 20 A typical @ 3V, 32 kHz - < typical standby current © 2006 Microchip Technology Inc. PIC16F872 with 10-bit A/D Pin Diagram DIP, SOIC, SSOP MCLR/V PP RA0/AN0 RA1/AN1 ...
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... Index ................................................................................................................................................................................................. 157 On-Line Support................................................................................................................................................................................ 163 Reader Response ............................................................................................................................................................................. 164 PIC16F872 Product Identification System ........................................................................................................................................ 165 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... Microchip Technology Inc. PIC16F872 document to this data sheet, and is highly recom- mended reading for a better understanding of the device architecture and operation of the peripheral modules. The block diagram of the PIC16F872 architecture is shown in Figure 1-1. A pinout description is provided in Table 1- MHz POR, BOR (PWRT, OST) 2K ...
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... PIC16F872 FIGURE 1-1: PIC16F872 BLOCK DIAGRAM 13 Program Counter FLASH Program Memory Program 14 Bus Instruction reg Direct Addr 8 Instruction Start-up Timer Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Low Voltage Programming MCLR Timer0 Timer1 Data EEPROM CCP Note 1: Higher order bits are from the STATUS register. ...
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... TABLE 1-2: PIC16F872 PINOUT DESCRIPTION I/O/P Pin Name Pin# Type OSC1/CLKI 9 I OSC1 CLKI OSC2/CLKO 10 O OSC2 CLKO MCLR/V 1 I/P PP MCLR V PP RA0/AN0 2 I/O RA0 AN0 RA1/AN1 3 I/O RA1 AN1 RA2/AN2 I/O REF RA2 AN2 V - REF RA3/AN3 I/O REF RA3 AN3 ...
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... PIC16F872 TABLE 1-2: PIC16F872 PINOUT DESCRIPTION (CONTINUED) I/O/P Pin Name Pin# Type RB0/INT 21 I/O RB0 INT RB1 22 I/O RB2 23 I/O RB3/PGM 24 I/O RB3 PGM RB4 25 I/O RB5 26 I/O RB6/PGC 27 I/O RB6 PGC RB7/PGD 28 I/O RB7 PGD RC0/T1OSO/T1CKI 11 I/O RC0 T1OSO T1CKI ...
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... MEMORY ORGANIZATION There are three memory blocks in the PIC16F872. The Program Memory and Data Memory have separate buses so that concurrent access can occur. Data mem- ory is covered in this section; the EEPROM data mem- ory and FLASH program memory blocks are detailed in Section 3 ...
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... PIC16F872 FIGURE 2-2: PIC16F872 REGISTER FILE MAP File Address (*) Indirect addr. Indirect addr. 00h 01h OPTION_REG TMR0 02h PCL STATUS 03h FSR 04h 05h PORTA 06h PORTB PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh PIR2 TMR1L 0Eh ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 39, 94 SSPEN CKP SSPM3 SSPM2 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 45, 94 CHS2 CHS1 CHS0 GO/ DONE PIC16F872 Value on: Details Bit 1 Bit 0 POR, on BOR page: 0000 0000 21, 93 xxxx xxxx 35, 93 0000 0000 20 ...
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... PIC16F872 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (2) 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RBPU INTEDG (2) 82h PCL Program Counter (PC) Least Significant Byte (2) 83h STATUS ...
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... PS2 RP0 — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93 TMR0IE INTE RBIE TMR0IF — — WRERR WREN PIC16F872 Value on: Details Bit 1 Bit 0 POR, on BOR page: 0000 0000 21, 93 xxxx xxxx 35, 93 0000 0000 20 0001 1xxx 12, 93 xxxx xxxx 21, 93 — ...
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... PIC16F872 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...
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... TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA PS2 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 R/W-1 R/W-1 PS1 PS0 bit Bit is unknown DS30221C-page 13 ...
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... PIC16F872 2.2.2.3 INTCON Register The INTCON Register is a readable and writable regis- ter, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh) ...
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... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 ADIE reserved reserved SSPIE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 R/W-0 R/W-0 R/W-0 CCP1IE TMR2IE TMR1IE bit Bit is unknown DS30221C-page 15 ...
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... PIC16F872 2.2.2.5 PIR1 Register The PIR1 register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: PIR1 REGISTER (ADDRESS: 0Ch) R/W-0 R/W-0 reserved ADIF bit 7 bit 7 Reserved: Always maintain these bits clear bit 6 ADIF: A/D Converter Interrupt Flag bit ...
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... R = Readable bit - n = Value at POR © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-0 U-0 — EEIE BCLIE — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 U-0 R/W-0 — reserved bit Bit is unknown DS30221C-page 17 ...
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... PIC16F872 2.2.2.7 PIR2 Register The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt. . REGISTER 2-7: PIR2 REGISTER (ADDRESS: 0Dh) U-0 R/W-0 — reserved bit 7 bit 7 Unimplemented: Read as '0' ...
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... BODEN bit in the Configuration Word). U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 U-0 R/W-0 R/W-1 — POR BOR bit Bit is unknown DS30221C-page 19 ...
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... When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. Since the PIC16F872 has only 2K words of program memory or one page, additional code is not required to ensure that the correct page is selected before a CALL or GOTO instruction is exe- cuted. The PCLATH< ...
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... IRP Bank Select 80h 100h 180h FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 PIC16F872 INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR,F ;inc pointer ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 FSR Register Location Select DS30221C-page 21 ...
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... PIC16F872 NOTES: DS30221C-page 22 © 2006 Microchip Technology Inc. ...
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... Data memory, the EEADR register holds the address to be accessed. Depending on the operation, the EEDATA register holds the data to be written or the data read at the address in EEADR. The PIC16F872 has 64 bytes of EEPROM Data memory and therefore, requires that the two Most Significant bits of EEADR remain clear. ...
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... PIC16F872 Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation will be disabled. Therefore, the WREN bit must be set before executing a write operation ...
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... Data memory ;Enable writes ;Only disable interrupts ;if already enabled, ;otherwise discard ;Write 55h to ;EECON2 ;Write AAh to ;EECON2 ;Start write operation ;Only enable interrupts ;if using interrupts, ;otherwise discard ;Disable writes PIC16F872 DS30221C-page 25 ...
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... PIC16F872 3.4 Reading the FLASH Program Memory Reading FLASH Program memory is much like that of EEPROM Data memory, only two NOP instructions must be inserted after the RD bit is set. These two instruction cycles that the NOP instructions execute will be used by the microcontroller to read the data out of program memory and insert the value into the EEDATH:EEDATA registers ...
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... On power-up, the WREN bit is cleared and the Power-up Timer (if enabled) prevents writes. The write initiate sequence and the WREN bit together help prevent any accidental writes during brown-out, power glitches or firmware malfunction. PIC16F872 DS30221C-page 27 ...
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... The state of the program memory code protect bits, CP0 and CP1, do not affect the execution of instruc- tions out of program memory. The PIC16F872 can always read the values in program memory, regardless of the state of the code protect bits. However, the state of the code protect bits and the WRT bit will have differ- ...
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... I/O PORTS The PIC16F872 provides three general purpose I/O ports. Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. ...
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... PIC16F872 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 bit0 TTL RA1/AN1 bit1 TTL RA2/AN2 bit2 TTL RA3/AN3/V bit3 TTL REF RA4/T0CKI bit4 ST RA5/SS/AN4 bit5 TTL Legend: TTL = TTL input Schmitt Trigger input TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address ...
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... SS Set RBIF From other RB7:RB4 pins RB7:RB6 In Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). PIC16F872 BLOCK DIAGRAM OF RB7:RB4 PINS V DD Weak P Pull-up Data Latch D Q (1) ...
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... PIC16F872 TABLE 4-3: PORTB FUNCTIONS Name Bit# Buffer (1) RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL RB3/PGM bit3 TTL RB4 bit4 TTL RB5 bit5 TTL (2) RB6/PGC bit6 TTL/ST (2) RB7/PGD bit7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
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... SSPl Input Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active (1) I/O pin and PIC16F872 PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<4:3> ( I/O 1 (1) Q pin CK Data Latch ...
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... PIC16F872 TABLE 4-5: PORTC FUNCTIONS Name Bit# Buffer Type RC0/T1OSO/T1CKI bit0 ST RC1/T1OSI/CCP2 bit1 ST RC2/CCP1 bit2 ST RC3/SCK/SCL bit3 ST RC4/SDI/SDA bit4 ST RC5/SDO bit5 ST RC6 bit6 ST RC7 bit7 ST Legend Schmitt Trigger input TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h ...
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... The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP SYNC Cycles PSA PRESCALER 8-bit Prescaler 1MUX PS2:PS0 PSA WDT Time-out PIC16F872 Source Edge Select bit T0SE Data Bus 8 TMR0 reg Set Flag Bit TMR0IF on Overflow DS30221C-page 35 ...
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... PIC16F872 5.2 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... Shaded cells are not used by Timer0. © 2006 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PEIE TMR0IE INTE RBIE TMR0IF INTF T0SE PSA PS2 PIC16F872 Value on: Value on Bit 1 Bit 0 POR, all other BOR resets xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u ...
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... PIC16F872 NOTES: DS30221C-page 38 © 2006 Microchip Technology Inc. ...
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... PICmicro™ Mid-range MCU Family Reference Manual (DS33023). U-0 R/W-0 R/W-0 R/W-0 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 R/W-0 R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown DS30221C-page 39 ...
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... PIC16F872 6.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is F /4. The synchronize control bit T1SYNC OSC (T1CON<2>) has no effect since the internal clock is always in sync. FIGURE 6-1: TIMER1 INCREMENTING EDGE ...
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... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. © 2006 Microchip Technology Inc. PIC16F872 TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq ...
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... PIC16F872 TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Address Name Bit 7 Bit 6 0Bh,8Bh, INTCON GIE PEIE TMR0IE 10Bh, 18Bh 0Ch PIR1 (3) ADIF 8Ch PIE1 (3) ADIE 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...
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... Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 TIMER2 BLOCK DIAGRAM (1) Prescaler TMR2 reg F /4 OSC 1:1, 1:4, 1:16 ...
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... PIC16F872 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written. ...
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... PWM U-0 R/W-0 R/W-0 R/W-0 — CCP1X CCP1Y CCP1M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 CCP MODE - TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 ...
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... PIC16F872 8.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge The type of event is configured by control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 PIC16F872 Value on: Value on Bit 1 Bit 0 POR, all other BOR RESETS INTF RBIF 0000 000x 0000 000u ...
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... PIC16F872 8.3 PWM Mode (PWM) In Pulse Width Modulation mode, the CCP1 pin pro- duces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE RBIE TMR0IF (1) (1) SSPIF CCP1IF (1) (1) SSPIE CCP1IE CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 PIC16F872 78.12kHz 156.3 kHz 208.3 kHz 3Fh 1Fh 17h 8 7 5.5 Value on: Value on Bit 1 Bit 0 POR, all other BOR ...
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... PIC16F872 NOTES: DS30221C-page 50 © 2006 Microchip Technology Inc. ...
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... C modes are covered in Section 9.2, while special considerations for connect- 2 ing the I C bus are discussed in Section 9.3. © 2006 Microchip Technology Inc. PIC16F872 The MSSP module is controlled by three special func- tion registers: • SSPSTAT • SSPCON • SSPCON2 The SSPSTAT and SSPCON registers are used in both ...
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... PIC16F872 REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 R/W-0 SMP bit 7 bit 7 SMP: Sample bit SPI Master mode Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode ...
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... R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 2 C conditions were not valid /4 OSC /16 OSC /64 OSC / (4 * (SSPADD+1) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown DS30221C-page 53 ...
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... PIC16F872 REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS: 91h) R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 7 GCEN: General Call Enable bit ( Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I ...
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... RA5 is configured as a digital I/O Any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (TRIS) register to the opposite value. © 2006 Microchip Technology Inc. PIC16F872 FIGURE 9-1: MSSP BLOCK DIAGRAM (SPI MODE) Read Write ...
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... PIC16F872 The clock polarity is selected by appropriately program- ming bit CKP (SSPCON<4>). This, then, would give waveforms for SPI communication as shown in Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • ...
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... INTF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 SSPM2 SSPM1 D R/W UA PIC16F872 bit2 bit1 bit0 bit0 bit1 bit0 bit0 Value on: Value on Bit 0 POR, all other BOR RESETS RBIF 0000 000x 0000 000u ...
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... PIC16F872 2 9.2 MSSP I C Operation 2 The MSSP module mode, fully implements all master and slave functions (including general call sup- port) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master func- tion). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7-9 for slave transmitter: © 2006 Microchip Technology Inc. PIC16F872 1. Receive first (high) byte of Address (bits SSPIF, BF and UA (SSPSTAT<1>) are set). 2. ...
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... PIC16F872 TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received BF SSPOV SSPSR Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 9.2.1.3 Slave Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 9-8). Address is compared to General Call Address after ACK, set interrupt flag R ACK Cleared in software SSPBUF is read PIC16F872 R Transmitting Data Not ACK From SSP Interrupt ...
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... PIC16F872 9.2.3 SLEEP OPERATION 2 While in SLEEP mode, the I C module can receive addresses or data. When an address match or com- plete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). TABLE 9-3: REGISTERS ASSOCIATED WITH I Address Name Bit 7 Bit 6 0Bh, 8Bh, ...
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... Clock Arbitration Reset ACKSTAT, PEN (SSPCON2) State Counter for End of XMIT/RCV The states where arbitration can be lost are: • Address Transfer • Data Transfer • A START Condition • A Repeated START Condition 2 C • An Acknowledge Condition PIC16F872 SSPM3:SSPM0, SSPADD<6:0> Baud Rate Generator DS30221C-page 63 ...
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... PIC16F872 2 9.2 MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Once Master mode is enabled, the user has six options. • Assert a START condition on SDA and SCL. • Assert a Repeated START condition on SDA and SCL. • ...
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... Set S bit (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit T T BRG BRG Write to SSPBUF occurs here 1st Bit T BRG S PIC16F872 03h 02h 2 C module is reset into its IDLE state. 2nd Bit T BRG DS30221C-page 65 ...
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... PIC16F872 2 9.2. MASTER MODE REPEATED START CONDITION TIMING A Repeated START condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sam- pled low, the baud rate generator is loaded with the contents of SSPADD< ...
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... SSPBUF takes place, holding SCL low and allowing SDA to float. © 2006 Microchip Technology Inc. PIC16F872 9.2.11.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out ...
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... PIC16F872 2 FIGURE 9-14 MASTER MODE TIMING (TRANSMISSION 10-BIT ADDRESS) DS30221C-page 68 © 2006 Microchip Technology Inc. ...
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... The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). © 2006 Microchip Technology Inc. PIC16F872 9.2.12.1 BF Status Flag In receive operation set when an address or data byte is loaded into SSPBUF from SSPSR cleared when SSPBUF is read ...
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... PIC16F872 2 FIGURE 9-15 MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS) DS30221C-page 70 © 2006 Microchip Technology Inc. ...
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... WCOL Status Flag If the user writes the SSPBUF when a STOP sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). BRG PIC16F872 . The SCL pin is then pulled low. Fol- BRG Cleared in software DS30221C-page 71 ...
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... PIC16F872 FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, set PEN Falling edge of 9th clock SCL ACK SDA SDA asserted low before rising edge of clock to setup STOP condition. Note one baud rate generator period. BRG 9.2.15 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit, or Repeated START/STOP condi- tion, de-asserts the SCL pin (SCL allowed to float high) ...
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... IDLE and the S and P bits are cleared. Sample SDA. While SCL is high, SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master PIC16F872 2 C Set bus collision interrupt DS30221C-page 73 ...
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... PIC16F872 9.2.18.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 9-20). b) SCL is sampled low before SDA is asserted low. (Figure 9-21). During a START condition, both the SDA and the SCL pins are monitored ...
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... SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG s SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF PIC16F872 Interrupts cleared in software '0' '0' Interrupts cleared in software. DS30221C-page 75 ...
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... PIC16F872 9.2.18.2 Bus Collision During a Repeated START Condition During a Repeated START condition, a bus collision occurs if low level is sampled on SDA when SCL goes from low level to high level. b) SCL goes low before SDA is asserted low, indi- cating that another master is attempting to trans- mit a data ’ ...
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... If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is a case of another master attempting to drive a data '0' (Figure 9-25). T BRG T BRG BRG SCL goes low before SDA goes high, set BCLIF PIC16F872 SDA sampled T BRG low after T , BRG set BCLIF '0' '0' T ...
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... PIC16F872 9.3 Connection Considerations for I Bus 2 For standard mode I C bus devices, the values of resistors R and R in Figure 9-27 depend on the fol lowing parameters: • Supply voltage • Bus capacitance • Number of connected devices (input current + leakage current). The supply voltage limits the minimum value of resistor ...
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... PICmicro™ Mid-Range MCU Family Ref- erence Manual (DS33023). R/W-0 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 GO/DONE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC16F872 U-0 R/W-0 — ADON bit Bit is unknown DS30221C-page 79 ...
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... PIC16F872 REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh) U-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’ Left justified. Six Least Significant bits of ADRESL are read as ‘0’. bit 6-4 ...
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... ADIF if required. 7. For the next conversion step 1 or step 2, as required. The A/D conversion time per bit is defined as T CHS2:CHS0 V AIN (Input Voltage PCFG3:PCFG0 - V SS PCFG3:PCFG0 PIC16F872 A/D Result register pair . AD 100 RA5/AN4 011 RA3/AN3/V + REF 010 RA2/AN2/V - REF ...
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... PIC16F872 10.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (R ) and the internal sampling ...
Page 85
... Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to con- sume current that is out of the device specifications ADCS1:ADCS0 time but can vary between 2 PIC16F872 will be converted. OL Maximum Device Frequency 1.25 MHz 5 MHz 20 MHz (Note 1) DS30221C-page 83 ...
Page 86
... PIC16F872 10.4 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers) ...
Page 87
... CCP1IF (1) (1) SSPIE CCP1IE CHS1 CHS0 GO/DONE — — PCFG3 PCFG2 PORTA Data Direction Register PORTA Data Latch when written: PORTA pins when read PIC16F872 for a Power-on Reset. The POR, MCLR, Bit 1 Bit 0 BOR WDT INTF RBIF 0000 000x 0000 000u ...
Page 88
... PIC16F872 NOTES: DS30221C-page 86 © 2006 Microchip Technology Inc. ...
Page 89
... SPECIAL FEATURES OF THE CPU The PIC16F872 microcontroller has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protec- tion. These are: • Oscillator Selection • RESET - Power-on Reset (POR) ...
Page 90
... PIC16F872 REGISTER 11-1: CONFIGURATION WORD (ADDRESS: 2007h) R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1 R/P-1 CP1 CP0 DEBUG — WRT bit13 bit 13-12 CP1:CP0: FLASH Program Memory Code Protection bits 11 = Code protection off bit 5 Not supported 01 = Not supported 00 = All memory code protected ...
Page 91
... Oscillator Configurations 11.2.1 OSCILLATOR TYPES The PIC16F872 can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC Resistor/Capacitor 11 ...
Page 92
... C values. The user also needs to take into account EXT 15 pF variation due to tolerance of external R and C compo- nents used. Figure 11-3 shows how the R/C combina tion is connected to the PIC16F872. 15-33 pF 15-33 pF FIGURE 11- EXT ± 20 PPM ± ...
Page 93
... Reset The PIC16F872 differentiates between various kinds of RESET: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during SLEEP • WDT Reset (during normal operation) • WDT Wake-up (during SLEEP) • Brown-out Reset (BOR) Some registers are not affected in any RESET condi- tion ...
Page 94
... If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution imme- diately. This is useful for testing purposes or to synchro- nize more than one PIC16F872 device operating in parallel. Table 11-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 11-6 shows the RESET conditions for all the registers ...
Page 95
... PIC16F872 STATUS PCON Register Register 0001 1xxx ---- --0x 000u uuuu ---- --uu 0001 0uuu ---- --uu 0000 1uuu ---- --uu uuu0 0uuu ---- --uu ...
Page 96
... PIC16F872 TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 OPTION_REG TRISA TRISB TRISC PIE1 PIE2 PCON SSPCON2 PR2 SSPADD SSPSTAT ADRESL ADCON1 EEDATA EEADR EEDATH EEADRH EECON1 EECON2 ...
Page 97
... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET © 2006 Microchip Technology Inc. PIC16F872 DD T PWRT T OST T PWRT T OST VIA RC NETWORK) ): CASE 1 DD DS30221C-page 95 ...
Page 98
... PIC16F872 FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-8: SLOW RISETIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30221C-page 96 T PWRT VIA RC NETWORK PWRT T OST ): CASE 2 ...
Page 99
... Interrupts The PIC16F872 has 10 sources of interrupt. The inter- rupt control register (INTCON) records individual inter- rupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON< ...
Page 100
... Typically, users may wish to save key reg- isters during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. Since the upper 16 bytes of each bank are common in PIC16F872 devices, temporary holding registers, W_TEMP, STATUS_TEMP should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- text save and restore ...
Page 101
... Postscaler MUX PSA 0 1 MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) BODEN CP1 CP0 PWRTE INTEDG T0CS T0SE PSA PIC16F872 PS2:PS0 To TMR0 (Figure 5-1) PSA Bit 2 Bit 1 Bit 0 (1) WDTE FOSC1 FOSC0 PS2 PS1 PS0 DS30221C-page 99 ...
Page 102
... PIC16F872 11.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance) ...
Page 103
... These locations are not accessible during normal execution, but are read- able and writable during program/verify recom- mended that only the 4 Least Significant bits of the ID location are used GND PIC16F872 (Note 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) ...
Page 104
... PIC16F872 11.17 In-Circuit Serial Programming PIC16F872 microcontrollers can be serially pro- grammed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product ...
Page 105
... NOP. Note: To maintain upward compatibility with future PIC16F872 products, do not use the OPTION and TRIS instructions. All instruction examples use the format ‘0xhh’ to repre- sent a hexadecimal number, where ‘h’ signifies a hexa- decimal digit ...
Page 106
... PIC16F872 TABLE 12-2: PIC16F872 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 107
... BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSS Syntax: k Operands: Operation: Status Affected: Description: BTFSC Syntax: f,d Operands: Operation: Status Affected: Description: PIC16F872 Bit Clear f [ label ] BCF f 127 (f<b>) None Bit 'b' in register 'f' is cleared. Bit Set f [ label ] BSF f 127 0 ...
Page 108
... PIC16F872 CALL Call Subroutine Syntax: [ label ] CALL k Operands 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) Status Affected: None Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immedi- ate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH ...
Page 109
... Operation: ( (destination) Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'. © 2006 Microchip Technology Inc. PIC16F872 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands 127 d [0,1] Operation: ( (destination), ...
Page 110
... PIC16F872 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register f are moved to a destination dependant upon the status destination is W register the destination is file register f itself useful to test a file register, since status flag Z is affected. ...
Page 111
... Description: The contents of register 'f' are rotated one bit to the right through the Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f © 2006 Microchip Technology Inc. PIC16F872 SLEEP Syntax: [ label ] SLEEP Operands: None Operation: 00h WDT, 0 ...
Page 112
... PIC16F872 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register 'f' are exchanged the result is placed in the W register the result is placed in register 'f'. XORLW Exclusive OR Literal with W ...
Page 113
... Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers pro- vide symbol information that is compatible with the MPLAB IDE memory display. PIC16F872 DS30221C-page 111 ...
Page 114
... PIC16F872 13.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for pre- compiled code to be used with the MPLINK object linker ...
Page 115
... Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I and separate headers for connection to an LCD module and a keypad. and PIC16F872 PIC16C62X, PIC16C71, PIC16C8X, that supports the ...
Page 116
... PIC16F872 13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple dem- onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Mod- ule. All the necessary hardware and software is included to run the basic demonstration programs ...
Page 117
... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16C8X PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers © 2006 Microchip Technology Inc. PIC16F872 Kits Eval and Boards Demo DS30221C-page 115 ...
Page 118
... PIC16F872 NOTES: DS30221C-page 116 © 2006 Microchip Technology Inc. ...
Page 119
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. (except V , MCLR. and RA4) ......................................... -0. (Note 2) .................................................................................................0 to +14V ) DD > ∑ PIC16F872 + 0.3V ∑ {( ∑( DS30221C-page 117 ) OL ...
Page 120
... PIC16F872 FIGURE 14-1: PIC16F872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V FIGURE 14-2: PIC16LF872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2 MHz Equation (6.0 MHz/V) (V MAX Equation (10.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro ...
Page 121
... DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) PIC16F872 (Commercial, Industrial) Param Symbol Characteristic/ No. Device V Supply Voltage DD D001 PIC16LF872 D001 PIC16F872 D001A PIC16LF872 D001A PIC16F872 D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on ...
Page 122
... PIC16F872 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) PIC16LF872 (Commercial, Industrial) PIC16F872 (Commercial, Industrial) Param Symbol Characteristic/ No. Device D015 I Brown-out BOR (6) Reset Current I Power-down Current PD D020 PIC16LF872 D020 PIC16F872 D021 PIC16LF872 D021 PIC16F872 D021A PIC16LF872 D021A PIC16F872 D023 I Brown-out ...
Page 123
... Note oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions ...
Page 124
... Note oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions ...
Page 125
... DC Characteristics: PIC16F872 (Extended) Param Symbol Characteristic/ No. Device V Supply Voltage DD D001 D001A D001A D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset signal D005 V Brown-out Reset ...
Page 126
... Note oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions ...
Page 127
... Note oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions ...
Page 128
... PIC16F872 14.5 Timing Parameter Symbology The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: ...
Page 129
... All specified values are PIC16F872 Units Conditions MHz XT and RC osc mode MHz HS osc mode (-04) MHz HS osc mode (-20) kHz LP osc mode MHz RC osc mode MHz XT osc mode ...
Page 130
... PIC16F872 FIGURE 14-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O Pin (input) I/O Pin old value (output) Note: Refer to Figure 14-3 for load conditions. TABLE 14-2: CLKOUT AND I/O TIMING REQUIREMENTS Param Symbol Characteristic No. 10* TosH2ckL OSC1 to CLKOUT 11* TosH2ckH OSC1 to CLKOUT ...
Page 131
... Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. PIC16F872 BOR 35 Min Typ† ...
Page 132
... PIC16F872 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI RC0/T1OSO/T1CKI TMR0 or TMR1 Note: Refer to Figure 14-3 for load conditions. TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width ...
Page 133
... Microchip Technology Inc Min 0. Standard(F) 10 Extended(LF Standard(F) 10 Extended(LF Standard(F) — Extended(LF) — Standard(F) — Extended(LF) — PIC16F872 Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1 ...
Page 134
... PIC16F872 FIGURE 14-10: SPI MASTER MODE TIMING (CKE = 0, SMP = SCK (CKP = 0) 71 SCK (CKP = 1) 80 SDO SDI MSb IN 73 Note: Refer to Figure 14-3 for load conditions. FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) MSb SDO SDI ...
Page 135
... SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 14-3 for load conditions. © 2006 Microchip Technology Inc MSb BIT6 - - - - - -1 75, 76 MSb IN BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb IN PIC16F872 LSb 77 LSb DS30221C-page 133 ...
Page 136
... PIC16F872 TABLE 14-6: SPI MODE REQUIREMENTS Param Symbol No. 70* TssL2scH SCK or SCK Input TssL2scL 71* TscH SCK Input High Time (Slave mode) 72* TscL SCK Input Low Time (Slave mode) 73* TdiV2scH, Setup Time of SDI Data Input to SCK Edge TdiV2scL 74* TscH2diL, Hold Time of SDI Data Input to SCK Edge ...
Page 137
... PIC16F872 102 92 110 Units Conditions s Device must operate at a mini- mum of 1.5 MHz s Device must operate at a mini- mum of 10 MHz s Device must operate at a mini- mum of 1 ...
Page 138
... PIC16F872 TABLE 14-9: A/D CONVERTER CHARACTERISTICS: PIC16F872 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LF872 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution R A03 E Integral Linearity Error IL A04 E Differential Linearity Error DL A06 E Offset Error OFF A07 E Gain Error GN A10 — Monotonicity A20 V Reference Voltage ( REF REF ...
Page 139
... T /2 § — OSC cycle. CY PIC16F872 NEW_DATA DONE Units Conditions s T based, V 3.0V OSC REF s T based, V 2.0V OSC REF s A/D RC mode s A/D RC mode T ...
Page 140
... PIC16F872 NOTES: DS30221C-page 138 © 2006 Microchip Technology Inc. ...
Page 141
... FIGURE 15-2: MAXIMUM Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) 7 Minimum: mean – 3 (-40°C to 125° . © 2006 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC 3.5V 3. vs. F OVER V (HS MODE) OSC . PIC16F872 DS30221C-page 139 ...
Page 142
... PIC16F872 FIGURE 15-3: TYPICAL I DD 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 FIGURE 15-4: MAXIMUM I DD 2.0 Typical: statistical mean @ 25°C 1.8 Maximum: mean + 3 (-40° ...
Page 143
... Minimum: mean – 3 (-40°C to 125°C) 100 © 2006 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC (kHz) OSC vs. F OVER V (LP MODE) OSC (kHz) OSC PIC16F872 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. 100 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. 100 DS30221C-page 141 ...
Page 144
... PIC16F872 FIGURE 15-7: AVERAGE F OSC (RC MODE pF 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 FIGURE 15-8: AVERAGE F OSC (RC MODE 100 pF 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 DS30221C-page 142 vs. V FOR VARIOUS VALUES ...
Page 145
... Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.3k 5.1k 10k 100k 3.0 3.5 4.0 V (V) DD Max (125°C) Max (125C) Max (85°C) Max (85C) Typ (25°C) Typ (25C) 3.0 3.5 4.0 V (V) DD PIC16F872 4.5 5.0 5.5 4.5 5.0 5.5 DS30221C-page 143 ...
Page 146
... PIC16F872 FIGURE 15-11: I vs. V BOR DD 1.2 Typical: statistical mean @ 25°C 1.0 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 0.8 0.6 0.4 Device in RESET Device in Reset 0.2 0.0 2.2 2.0 2.5 3.0 FIGURE 15-12: TYPICAL AND MAXIMUM I ...
Page 147
... FIGURE 15-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs 2.0 2.5 3.0 © 2006 Microchip Technology Inc. PIC16F872 vs. V OVER TEMPERATURE WDT DD Max (125°C) Max (125C) Typ (25°C) Typ (25C) 3.5 4.0 4 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – ...
Page 148
... PIC16F872 FIGURE 15-15: AVERAGE WDT PERIOD vs 125°C 125C 40 35 85°C 85C 30 25°C 25C 25 20 -40°C -40C 2.2 2.0 2.5 FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM V 5.0 4.5 4.0 3.5 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – ...
Page 149
... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Typ (25°C) Typ (25C (-mA Max (125°C) Max (125C) Typ (25°C) Typ (25C) Min (-40°C) Min (-40C (-mA) OL PIC16F872 =3V, - +125 =5V, - 125 DS30221C-page 147 ...
Page 150
... PIC16F872 FIGURE 15-19: TYPICAL, MINIMUM AND MAXIMUM V 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.5 1.0 0.5 0 FIGURE 15-20: MINIMUM AND MAXIMUM V 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40° ...
Page 151
... Microchip Technology Inc. vs. V (ST INPUT, - +125 Max High Min High Max Low Min Low 3.5 4 INPUT, - +125 Max High Max Low 3.0 3.5 4.0 V (V) DD PIC16F872 4.5 5.0 5.5 Min High Min Low 4.5 5.0 5.5 DS30221C-page 149 ...
Page 152
... PIC16F872 NOTES: DS30221C-page 150 © 2006 Microchip Technology Inc. ...
Page 153
... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. PIC16F872 Example e 3 PIC16F872/SP 0610017 Example e PIC16F872-I/SO 3 0610017 Example PIC16LF872 e -I/SS 3 0610017 ...
Page 154
... PIC16F872 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane ...
Page 155
... L .016 .033 .050 .009 .011 .013 B .014 .017 .020 PIC16F872 A2 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 ...
Page 156
... PIC16F872 28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width ...
Page 157
... Interrupts 7 Communication Basic SSP 2 (SPI Slave) Frequency 20 MHz A/D 8-bit, 5 channels CCP 1 Program 2K EPROM Memory RAM 128 bytes EEPROM Data None Other DS30221C-page 155 PIC16F872 SSP (SPI Master/Slave) 20 MHz 10-bit 5 channels 1 2K FLASH 128 bytes 64 bytes In-Circuit Debugger, Low Voltage Programming ...
Page 158
... PIC16F872 NOTES: DS30221C-page 156 © 2006 Microchip Technology Inc. ...
Page 159
... I C Slave Mode ......................................................... 58 Interrupt Logic ............................................................ 97 MSSP (SPI Mode) ..................................................... 55 On-Chip Reset Circuit ................................................ 91 Peripheral Output Override (RC 2:0, 7:5) .................. 33 Peripheral Output Override (RC 4:3) ......................... 33 PIC16F872 .................................................................. 4 © 2006 Microchip Technology Inc. PWM Mode ............................................................... 48 RA3:RA0 and RA5 Pins ............................................ 29 RA4/T0CKI Pin .......................................................... 29 RB3:RB0 Pins ........................................................... 31 RB7:RB4 Pins ........................................................... 31 RC Oscillator Mode ................................................... 90 ...
Page 160
... PIC16F872 Code Protection ........................................................ 87 Compare Mode CCP Pin Configuration ............................................... 47 Timer1 Mode Selection .............................................. 47 Computed GOTO ............................................................... 20 Configuration Bits .............................................................. 87 Configuration Word ............................................................ 88 Conversion Considerations .............................................. 155 D D/A Bit ................................................................................ 52 Data EEPROM ................................................................... 23 Associated Registers ................................................. 28 Code Protection ......................................................... 28 Reading ..................................................................... 25 Special Functions Registers ...................................... 23 Spurious Write Protection .......................................... 27 Write Verify ................................................................ 27 Writing to .................................................................... 25 Data Memory ....................................................................... 7 Bank Select (RP1:RP0 Bits) ...
Page 161
... OPCODE Field Descriptions ........................................... 103 OPTION_REG Register ..............................................10 INTEDG Bit ............................................................... 13 PS2:PS0 Bits ............................................................. 13 PSA Bit ...................................................................... 13 RBPU Bit ................................................................... 13 T0CS Bit .................................................................... T0SE Bit .................................................................... 13 OSC1/CLKI Pin ................................................................... 5 OSC2/CLKO Pin .................................................................. 5 Oscillator Configuration HS .......................................................................89 LP ........................................................................89 RC ................................................................ 89 XT ........................................................................89 Oscillator Selection ............................................................ 87 Oscillator, WDT ................................................................. 99 Oscillators Capacitor Selection ................................................... 90 Crystal and Ceramic Resonators .............................. 89 RC ............................................................................. 90 PIC16F872 , DS30221C-page 159 ...
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... PIC16F872 P P Bit STOP Bit (P) .............................................................. 52 Packaging ............................................................... 151 PCL Register ..........................................................9 PCLATH Register ......................................................... 9 PCON Register .....................................................10 BOR Bit ...................................................................... 19 POR Bit ...................................................................... 19 PEN Bit STOP Condition Enable Bit (PEN) ............................. 54 PICDEM 1 Low Cost PICmicro Demonstration Board ............................................... 113 PICDEM 17 Demonstration Board ................................... 114 PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 113 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ...
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... START Condition ...................................... 75 Brown-out Reset ..................................................... 129 Bus Collision Transmit and Acknowledge ............................... Bus Collision During a Repeated START Condition (Case 1) .................................... Bus Collision During a Repeated START Condition (Case2) ..................................... Bus Collision During a STOP Condition (Case 1) .................................................... 77 Bus Collision During a STOP Condition (Case 2) .................................................... 77 PIC16F872 , DS30221C-page 161 ...
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... PIC16F872 Bus Collision During START Condition (SCL = 0) ................................................... 75 Bus Collision During START Condition (SDA Only) ................................................ 74 Capture/Compare/PWM .......................................... 131 CLKOUT and I/O ..................................................... 128 External Clock .......................................................... 127 First START Bit Timing .............................................. Bus Data ............................................................ 135 Bus START/STOP Bits ...................................... 134 Master Mode Transmission ................................. Mode (7-bit Reception) ................................. 60 ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC16F872 should contact their distributor, DS30221C-page 163 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F872 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... Pattern a) b) (2) ;V range 4. range 2.0V to 5.5V DD +85 C (Industrial) Note PIC16F872 PIC16F872 - I/P 301 = Industrial temp., skinny PDIP package, normal V limits, QTP pattern DD #301. PIC16F872 - E/SO = Extended temp., SOIC package, normal V limits. DD PIC16LF872 - /SS = Commercial temp., SSOP package, extended V limits ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...