ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet

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ISP1505CBSGE

Manufacturer Part Number
ISP1505CBSGE
Description
IC ULPI TRANSCEIVER 24-HVQFN
Manufacturer
ST-Ericsson Inc
Type
Transceiverr
Datasheet

Specifications of ISP1505CBSGE

Protocol
USB 2.0
Voltage - Supply
3 V ~ 4.5 V
Mounting Type
Surface Mount
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
For Use With
ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Other names
ISP1505CBS
ISP1505CBS
Dear customer,
As from August 2
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
Company name - NXP B.V. is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site -
Contact information - the list of sales offices previously obtained by sending
an email to
under Contacts.
http://www.nxp.com
salesaddresses@nxp.com
nd
2008, the wireless operations of NXP have moved to a new company,
IMPORTANT NOTICE
is replaced with
, is now found at
http://www.stnwireless.com
http://www.stnwireless.com
www.stnwireless.com

Related parts for ISP1505CBSGE

ISP1505CBSGE Summary of contents

Page 1

IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...

Page 2

ISP1505A; ISP1505C ULPI Hi-Speed USB host and peripheral transceiver Rev. 03 — 26 August 2008 1. General description The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification ...

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NXP Semiconductors I Highly optimized ULPI compliant N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1505ABS) and ...

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NXP Semiconductors 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1505ABS 05A 19.2 MHz [1] ISP1505CBS 05C 26 MHz [1] The package marking is the first line of text on the IC ...

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NXP Semiconductors 5. Block diagram 21 CLOCK 15 STP 14 DIR 16 NXT ULPI 1, 2, INTERFACE 17 to 20, 8 22, 24 DATA [7:0] 12 RESET_N/ PSW_N 10 XTAL1 11 XTAL2 CC(I/O) 9 REG3V3 13 REG1V8 ...

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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Type DATA1 1 I/O DATA0 2 I CC(I/O) RREF AI/O V ...

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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type RESET_N/PSW_N 12 I/O REG1V8 13 P DIR 14 O STP 15 I NXT 16 O DATA7 17 I/O DATA6 18 I/O DATA5 19 I/O DATA4 20 I/O CLOCK 21 ...

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NXP Semiconductors 7. Functional description 7.1 ULPI interface controller The ISP1505 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI interface ...

Page 9

NXP Semiconductors • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode • bus terminations on DP and DM for host and OTG modes For details on controlling resistor settings, see ...

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NXP Semiconductors While it is possible for the external 5 V supply to use the ISP1505 internal A_VBUS_VLD comparator, typical 5 V supplies must provide their own power fault indicator that can be connected as an input to the ISP1505 ...

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NXP Semiconductors 7.10.2 V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.10.3 RREF Resistor reference analog I/O pin. A ...

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NXP Semiconductors 7.10.7 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1505 internal digital and analog circuits, and must not be used to power external circuits. For correct operation of the regulator recommended ...

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NXP Semiconductors 7.10.10 DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1505 holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1505 listens for data ...

Page 14

NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1505 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one ...

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NXP Semiconductors Table 3. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1505 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that ...

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NXP Semiconductors Table 4. Signal mapping during low-power mode Signal Maps to Direction Reserved DATA2 O INT DATA3 O Reserved DATA[7:4] O 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and ...

Page 17

NXP Semiconductors Table 6. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than ...

Page 18

NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Host low-speed 10b suspend Host low-speed 10b resume Host Test J or Test K 00b Peripheral settings Peripheral chirp 00b Peripheral 00b ...

Page 19

NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1505. 9.1 ULPI references The ISP1505 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin ...

Page 20

NXP Semiconductors If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1505 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 4. ...

Page 21

NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1505. The ISP1505 regulator starts to turn on. CC ...

Page 22

NXP Semiconductors The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1505 will ...

Page 23

NXP Semiconductors The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD. 9.5 TXCMD and RXCMD Commands between the ISP1505 and the link ...

Page 24

NXP Semiconductors Table 9. RXCMD byte format DATA Name Description and value LINESTATE LINESTATE signals: For a definition of LINESTATE, see DATA0 — LINESTATE[0] DATA1 — LINESTATE[ state Encoded V BUS 5 to ...

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NXP Semiconductors Table 11. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates ...

Page 26

NXP Semiconductors V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 7. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the ...

Page 27

NXP Semiconductors OTG devices: that supplies less than 100 pin. The internal A_VBUS_VLD comparator can be used. If the OTG A-device provides more than 100 USB host controllers” on page 25 detect when an ...

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NXP Semiconductors 9.6 Register read and write operations Figure 8 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1505 unexpectedly asserts DIR during the operation. When ...

Page 29

NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 ...

Page 30

NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR ...

Page 31

NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD ...

Page 32

NXP Semiconductors Table 16. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK D ...

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NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 12. High-speed receive-to-transmit packet timing 9.9 ...

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NXP Semiconductors CLOCK DATA[7: Fig 13. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed and low-speed host-initiated suspend and resume Figure 14 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note ...

Page 35

NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 14. Full-speed suspend and ...

Page 36

NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1505 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN ...

Page 37

NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM ...

Page 38

NXP Semiconductors 9.10.3 Remote wake-up The ISP1505 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of ...

Page 39

NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 16. Remote ...

Page 40

NXP Semiconductors PHY will not transmit any EOP. The ISP1505 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the ...

Page 41

NXP Semiconductors 9.12.1 OTG comparators The ISP1505 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V B_SESS_VLD are communicated to the link by RXCMDs as described in comparators ...

Page 42

NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 18. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 ...

Page 43

NXP Semiconductors 9.14 Aborting transfers The ISP1505 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 . 9.15 Avoiding contention on the ULPI data bus Because the ULPI ...

Page 44

NXP Semiconductors 10. Register map Table 17. Immediate register set overview Field name Immediate register set Vendor ID Low register Vendor ID High register Product ID Low register Product ID High register Function Control register Interface Control register OTG Control ...

Page 45

NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 19 Table 19. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access Value VENDOR_ID_ ...

Page 46

NXP Semiconductors Table 24. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the ...

Page 47

NXP Semiconductors Table 26. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1505 to protect ...

Page 48

NXP Semiconductors Table 28. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_VBUS_ Use External V IND 0b — Use the internal OTG comparator. ...

Page 49

NXP Semiconductors Table 30. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved 3 SESS_END_R Session End Rise: ...

Page 50

NXP Semiconductors Table 34. USB Interrupt Status register (address R = 13h) bit description Bit Symbol SESS_END 2 SESS_VALID 1 VBUS_VALID 0 HOST_DISCON 10.1.8 USB Interrupt Latch register The bits of the USB Interrupt Latch ...

Page 51

NXP Semiconductors Table 38. Debug register (address R = 15h) bit description Bit Symbol LINESTATE1 0 LINESTATE0 10.1.10 Scratch register Table 39 purposes. Table 39. Scratch register (address R = 16h to 18h ...

Page 52

NXP Semiconductors Table 41. Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic 1 to ...

Page 53

NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from V ...

Page 54

NXP Semiconductors 12. Limiting values Table 42. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I ...

Page 55

NXP Semiconductors 14. Static characteristics Table 44. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter ...

Page 56

NXP Semiconductors Table 45. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N CC(I/O) Typical values are 3 ...

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NXP Semiconductors Table 47. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter ...

Page 58

NXP Semiconductors Table 48. Static characteristics CC(I/O) Typical values are 3 Symbol Parameter V A-device V A_VBUS_VLD ...

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NXP Semiconductors 15. Dynamic characteristics Table 51. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 Symbol ...

Page 60

NXP Semiconductors Table 52. Dynamic characteristics: digital I/O pins +85 C; unless otherwise specified. CC amb Symbol Parameter t DATA output delay with respect d(DATA) to the rising ...

Page 61

NXP Semiconductors Table 53. Dynamic characteristics: analog I/O pins (DP CC(I/O) Symbol Parameter t transition time: fall time LF t rise and fall ...

Page 62

NXP Semiconductors HSR Fig 21. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential ...

Page 63

NXP Semiconductors 16. Application information Table 54. Recommended bill of materials [1] Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG D ...

Page 64

V IN FAULT R pullup V BUS SWITCH ON OUT V BUS GND USB 4 STANDARD-A RECEPTACLE SHIELD 5 C VBUS A1 SHIELD 6 IP4359CX4/LF SHIELD B1 7 SHIELD 8 (1) Frequency is version ...

Page 65

R VBUS V BUS USB GND 4 STANDARD-B RECEPTACLE A1 A2 SHIELD 5 IP4359CX4/LF SHIELD ESD SHIELD 7 SHIELD C VBUS 8 f i(XTAL1) (1) Frequency is version dependent: ISP1505ABS: 19.2 ...

Page 66

NXP Semiconductors 17. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area ...

Page 67

NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction ...

Page 68

NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 69

NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 57. Acronym ASIC ATX CD-RW EOP ESD ESR FS ...

Page 70

NXP Semiconductors Table 57. Acronym PID PLD PLL POR RoHS RXCMD SE0 SOF SRP STB SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification ...

Page 71

NXP Semiconductors 21. Revision history Table 58. Revision history Document ID Release date ISP1505A_ISP1505C_3 20080826 • Modifications: Changed On-The-Go Supplement to the USB 2.0 Specification from Rev. 1.2 to Rev. 1.3. • Section 2 • Section 8.2 “USB and OTG ...

Page 72

NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 73

NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...

Page 74

NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...

Page 75

NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

Page 76

NXP Semiconductors 10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 44 10.1.2 Function Control register . . . . . . . . . . . ...

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