ICS1893BFILFT IDT, Integrated Device Technology Inc, ICS1893BFILFT Datasheet
ICS1893BFILFT
Specifications of ICS1893BFILFT
Related parts for ICS1893BFILFT
ICS1893BFILFT Summary of contents
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Integrated Device Technology, Inc. 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™ General The ICS1893BF is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base- ...
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ICS1893BF Data Sheet - Release Section Chapter 1 Abbreviations and Acronyms ......................................................................................... 10 Chapter 2 Conventions and Nomenclature..................................................................................... 12 Chapter 3 Overview of the ICS1893BF............................................................................................. 14 3.1 100Base-TX Operation .......................................................................................... 15 3.2 10Base-T Operation ............................................................................................... 15 Chapter 4 Operating Modes ...
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ICS1893BF Data Sheet Rev Release Section 6.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 36 6.3.1 PCS Sublayer ........................................................................................................ 36 6.3.2 PMA Sublayer ........................................................................................................ 36 6.3.3 PCS/PMA Transmit Modules ................................................................................. 37 6.3.4 PCS/PMA Receive Modules .................................................................................. 37 ...
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ICS1893BF Data Sheet - Release Section Chapter 7 Management Register Set ............................................................................................... 49 7.1 Introduction to Management Register Set ............................................................. 50 7.1.1 Management Register Set Outline ......................................................................... 50 7.1.2 Management Register Bit Access .......................................................................... 51 7.1.3 Management Register Bit Default ...
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ICS1893BF Data Sheet Rev Release Section 7.5 Register 3: PHY Identifier Register ........................................................................ 63 7.5.1 OUI bits 19-24 (bits 3.15:10) .................................................................................. 63 7.5.2 Manufacturer's Model Number (bits 3.9:4) ............................................................. 63 7.5.3 Revision Number (bits 3.3:0) ................................................................................. 63 7.6 ...
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ICS1893BF Data Sheet - Release Section 7.11 Register 16: Extended Control Register ................................................................ 76 7.11.1 Command Override Write Enable (bit 16.15) ......................................................... 77 7.11.2 ICS Reserved (bits 16.14:11) ................................................................................. 77 7.11.3 PHY Address (bits 16.10:6) ................................................................................... 77 7.11.4 Stream Cipher ...
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ICS1893BF Data Sheet Rev Release Section 7.14 Register 19: Extended Control Register 2 ............................................................. 87 7.14.1 Node Configuration (bit 19.15) ............................................................................... 88 7.14.2 Hardware/Software Priority Status (bit 19.14) ........................................................ 88 7.14.3 Remote Fault (bit 19.13) ........................................................................................ 88 7.14.4 ...
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ICS1893BF Data Sheet - Release Section 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion ......123 9.5.15 Reset: Power-On Reset .......................................................................................124 9.5.16 Reset: Hardware Reset and Power-Down ...........................................................125 9.5.17 10Base-T: Heartbeat Timing (SQE) .....................................................................126 9.5.18 10Base-T: Jabber Timing .....................................................................................127 9.5.19 10Base-T: Normal ...
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ICS1893BF Data Sheet Rev Release Revision History • The initial release of this document, Rev A, is dated October 31, 2003 • Rev dated March 24, 2004. The following list indicates changes made. – Page 1. ...
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ICS1893BF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National ...
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ICS1893BF Data Sheet Rev Release Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OSI Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893BF is a physical-layer device, also referred to ...
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ICS1893BF Data Sheet - Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or signal) names ...
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ICS1893BF Data Sheet Rev Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1893BF, Rev. F, 5/13/10 Convention / Nomenclature • When ...
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ICS1893BF Data Sheet - Release Chapter 3 Overview of the ICS1893BF The ICS1893BF is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control) converts them into a serial bit stream, encodes them, and ...
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ICS1893BF Data Sheet Rev Release 3.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893BF accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893BF encapsulates each MAC frame, ...
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ICS1893BF Data Sheet - Release Chapter 4 Operating Modes Overview The ICS1893BF operating modes are typically controlled from software. The ICS1893BF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893BF is configured to ...
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ICS1893BF Data Sheet Rev Release 4.1 Reset Operations This section first discusses reset operations in general and then specific ways in which the ICS1893BF can be configured for various reset options. 4.1.1 General Reset Operations The following reset ...
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ICS1893BF Data Sheet - Release 4.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893BF can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893BF) • Software reset ...
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ICS1893BF Data Sheet Rev Release 4.1.2.3 Software Reset Entering Software Reset Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit 0.15. When this write occurs, the ICS1893BF enters the ...
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ICS1893BF Data Sheet - Release 4.3 Automatic Power-Saving Operations The ICS1893BF has power-saving features that automatically minimize its total power consumption while it is operating. Table 4-1 lists the ICS1893BF automatic power-saving features for the various modes. Table 4-1. Automatic ...
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ICS1893BF Data Sheet Rev Release 4.5 100Base-TX Operations The ICS1893BF 100Base-TX mode provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893BF is a 100M translator between a MAC ...
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ICS1893BF Data Sheet - Release 4.8 Auto-MDI/MDIX Crossover (New) The ICS1893BF includes the auto-MDI/MDIX crossover feature typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the CAT 5 ...
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ICS1893BF Data Sheet Rev Release Chapter 5 Interface Overviews The ICS1893BF MAC Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC-to-PHY interfaces: • Section 5.1, “MII Data ...
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ICS1893BF Data Sheet - Release 5.1 MII Data Interface The ICS1893BF’s MAC Interface is the Media Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893BF MAC Interface is configured for the MII Data Interface mode, data ...
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ICS1893BF Data Sheet Rev Release 5.2 Serial Management Interface The ICS1893BF provides an ISO/IEC compliant, two-wire Serial Management Interface as part of its MAC Interface. This Serial Management Interface is used to exchange control, status, and configuration information ...
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ICS1893BF Data Sheet - Release Figure 5-1. ICS1893BF Twisted Pair TP_AP 12 ICS1893BF TP_AN 13 Ideally, for these traces Z TP_BP 16 TP_BN 15 Ideally, for these traces Z ICS1893BF, Rev. F, 5/13/10 System Ground Plane 1:1 61.9Ω 1% Center ...
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ICS1893BF Data Sheet Rev Release 5.4 Clock Reference Interface The REF_IN pin provides the ICS1893BF Clock Reference Interface. The ICS1893BF requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is ...
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ICS1893BF Data Sheet - Release If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893BF. A pair of bypass capacitors on either side of the ...
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ICS1893BF Data Sheet Rev Release 5.5 Status Interface The ICS1893BF provides five multi-function configuration pins that report the results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table ...
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ICS1893BF Data Sheet - Release Figure 5-3 shows typical biasing and LED connections for the ICS1893BF. Figure 5-3. ICS1893BF LED - PHY Interface P4RD P3TD 8 6 REC 10KΩ 10KΩ This circuit decodes to PHY address = 1. Notes: 1. ...
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ICS1893BF Data Sheet Rev Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893BF functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS ...
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ICS1893BF Data Sheet - Release 6.1 Functional Block: Media Independent Interface All ICS1893BF MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893BF MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) ...
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ICS1893BF Data Sheet Rev Release 6.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893BF has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end ...
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ICS1893BF Data Sheet - Release 6. To indicate that the auto-negotiation process is complete, the ICS1893BF sets bits 1.5 and 17.4 high to logic one. After successful completion of the auto-negotiation process, the ICS1893BF Auto-Negotiation sublayer performs the following steps: ...
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ICS1893BF Data Sheet Rev Release 6.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893BF reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), ...
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ICS1893BF Data Sheet - Release 6.2.5 Auto-Negotiation: Progress Monitor Under typical circumstances, the Auto-Negotiation sublayer can establish a connection with the ICS1893BF’s remote link partner. However, some situations can prevent the auto-negotiation process from properly achieving this goal. For these ...
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ICS1893BF Data Sheet Rev Release 6.3.3 PCS/PMA Transmit Modules Both the PCS and PMA sublayers have Transmit modules. 6.3.3.1 PCS Transmit Module The ICS1893BF PCS Transmit module accepts nibbles from the MAC Interface and converts the nibbles into ...
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ICS1893BF Data Sheet - Release Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to the MAC Interface. Detection of an error forces the Receive state machine to assert the receive ...
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ICS1893BF Data Sheet Rev Release 6.3.6 4B/5B Encoding/Decoding The 4B/5B encoding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “code group”). There are 32 five-bit symbols, which include the following: • Of the 32 ...
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ICS1893BF Data Sheet - Release 6.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder When operating in the 100Base-TX mode, the ICS1893BF TP-PMD sublayer employs an MLT-3 encoder and decoder. During data transmission, the TP-PMD encoder converts the NRZI bit stream received from the ...
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ICS1893BF Data Sheet Rev Release 6.4.6 100Base-TX Operation: Twisted-Pair Receiver The ICS1893BF uses the same Twisted-Pair Receive pins (TP_RXP and TP_RXN) for both 10Base-T and 100Base-TX operations. The internal twisted-pair receiver modules interface with the medium through an ...
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ICS1893BF Data Sheet - Release During 10Base-T data reception, a Manchester Decoder translates the serial bit stream obtained from the Twisted-Pair Receiver (MDI) into an NRZ bit stream. The Manchester Decoder then passes the data to the MAC Interface in ...
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ICS1893BF Data Sheet Rev Release When the 10Base-T link is: • Invalid, and the Smart Squelch function is: – Disabled (bit 18.0 is logic one), the Link Monitor Function must detect at least one of the following events ...
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ICS1893BF Data Sheet - Release 6.5.7 10Base-T Operation: Carrier Detection The ICS1893BF has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state machines. These ...
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ICS1893BF Data Sheet Rev Release An ICS1893BF SQE Test Function is: • Enabled only when all the following conditions are true: – The ICS1893BF is in node mode. – The ICS1893BF is in half-duplex mode. – The ICS1893BF ...
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ICS1893BF Data Sheet - Release When an ICS1893BF detects a reversed signal polarity on its Twisted-Pair Receiver pins and the Auto Polarity-Inhibit bit is also logic zero (enabled), the ICS1893BF (1) automatically corrects the data stream and (2) sets its ...
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ICS1893BF Data Sheet Rev Release Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE periods are not part of the Management Frame Structure. Table 6-1. Management Frame Structure Summary Frame Field ...
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ICS1893BF Data Sheet - Release Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893BF compares the PHYAD field included within the management frame with the value of its PHYAD bits stored in register 16. (For ...
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ICS1893BF Data Sheet Rev Release Chapter 7 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, ...
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ICS1893BF Data Sheet - Release 7.1 Introduction to Management Register Set This section explains in general terms the Management Register set discussed in this chapter. (For a summary of the Management Register set, see 7.1.1 Management Register Set Outline This ...
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ICS1893BF Data Sheet Rev Release 7.1.2 Management Register Bit Access The ICS1893BF Management Registers include one or more of the following types of bits: Table 7-3. Description of Management Register Bit Types Management Register Bit Types Symbol Read-Only ...
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ICS1893BF Data Sheet - Release 7.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 7.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an ...
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ICS1893BF Data Sheet Rev Release 7.2 Register 0: Control Register Table 7-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes of the ICS1893BF. • The Control Register is accessible ...
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ICS1893BF Data Sheet - Release 7.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893BF. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair ...
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ICS1893BF Data Sheet Rev Release 7.2.5 Low Power Mode (bit 0.11) This bit provides one way to control the ICS1893BF low-power mode function. When bit 0.11 is logic: • Zero, there is no impact to ICS1893BF operations. • ...
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ICS1893BF Data Sheet - Release 7.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893BF Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). ...
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ICS1893BF Data Sheet Rev Release 7.3 Register 1: Status Register Table 7-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893BF and an STA. There are two types of status bits: ...
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ICS1893BF Data Sheet - Release 7.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893BF can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893BF must set bit 1.14 to logic: • ...
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ICS1893BF Data Sheet Rev Release 7.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893BF returns a logic zero. • Writes a reserved bit, ...
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ICS1893BF Data Sheet - Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893BF sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ...
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ICS1893BF Data Sheet Rev Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893BF detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893BF Jabber Detection ...
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ICS1893BF Data Sheet - Release 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893BF Data Sheet Rev Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is ...
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ICS1893BF Data Sheet - Release Table 7-9. PHY Identifier Register (Register 3 [0x03]) Bit Definition 3.11 OUI bit 3.10 OUI bit 3.9 Manufacturer’s Model Number bit 5 3.8 Manufacturer’s Model Number bit 4 3.7 ...
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ICS1893BF Data Sheet Rev Release 7.6 Register 4: Auto-Negotiation Register Table 7-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1893BF capabilities that it wants to advertise to its remote link ...
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ICS1893BF Data Sheet - Release 7.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read by an ...
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ICS1893BF Data Sheet Rev Release 7.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893BF transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits ...
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ICS1893BF Data Sheet - Release 7.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 7-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link ...
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ICS1893BF Data Sheet Rev Release 7.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893BF ...
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ICS1893BF Data Sheet - Release 7.8 Register 6: Auto-Negotiation Expansion Register Table 7-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 7-13. Auto-Negotiation ...
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ICS1893BF Data Sheet Rev Release 7.8.2 Parallel Detection Fault (bit 6.4) The ICS1893BF sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893BF cannot disseminate the ...
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ICS1893BF Data Sheet - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during ...
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ICS1893BF Data Sheet Rev Release 7.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports ...
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ICS1893BF Data Sheet - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word ...
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ICS1893BF Data Sheet Rev Release 7.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports ...
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ICS1893BF Data Sheet - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893BF provides to allow an STA to customize the operations of the device. Note: 1. For an ...
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ICS1893BF Data Sheet Rev Release 7.11.1 Command Override Write Enable (bit 16.15) The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write (CW) bits located throughout the MII Register set. A ...
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ICS1893BF Data Sheet - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893BF to transmit symbols that are typically classified as invalid. The purpose of this test bit ...
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ICS1893BF Data Sheet Rev Release 7.12 Register 17: Quick Poll Detailed Status Register Table 7-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed ...
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ICS1893BF Data Sheet - Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893BF is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software ...
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ICS1893BF Data Sheet Rev Release Note: An MDIO read of these bits provides a history of the greatest progress achieved by the auto-negotiation process. In addition, the MDIO read latches the present state of the Auto-Negotiation State Machine ...
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ICS1893BF Data Sheet - Release 7.12.6 False Carrier (bit 17.8) The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893BF in 100Base mode. A False Carrier occurs when the ICS1893BF begins evaluating potential ...
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ICS1893BF Data Sheet Rev Release 7.12.9 Premature End (bit 17.5) The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893BF. During reception of a valid packet, ...
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ICS1893BF Data Sheet - Release 7.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893BF activity while the ICS1893BF is operating in 10Base-T mode. Note: 1. For an ...
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ICS1893BF Data Sheet Rev Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893BF has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. ...
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ICS1893BF Data Sheet - Release 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893BF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, ...
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ICS1893BF Data Sheet Rev Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893BF operations. Note: 1. For an explanation of acronyms used in 2. During any write ...
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ICS1893BF Data Sheet - Release 7.14.1 Node Configuration (bit 19.15) The Node Configuration bit indicates the NOD/MODE. • In Node mode: – The SQE Test default setting is enabled. – The Carrier Sense signal (CRS) is asserted in response to ...
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ICS1893BF Data Sheet Rev Release Table 7-22. AMDIX_EN (Pin 10) and Control Bits 19. 9:8 AMDIX_EN (Pin 10) 1 Default Values: 1 Definitions: straight transmit = TP_AP & TP_AN receive = TP_BP & TP_BN cross transmit = TP_BP ...
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ICS1893BF Data Sheet - Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893BF Pin Diagram POAC 1 VSS 2 P1CL 3 P2LI 4 VSS 5 P3TD 6 VDD 7 P4RD 8 10/100 9 AMDIX_EN 10 VSS 11 TP_AP 12 ...
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ICS1893BF Data Sheet Rev Release 8.2 ICS1893BF Pin Descriptions Table 8-1. ICS1893BF MAC Interface Pins Signal Name MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 8-2. ICS 1893BF ...
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ICS1893BF Data Sheet - Release Table 8-3. ICS1893BF Configuration Pins Signal Name REF_IN REF_OUT RESETn 8.2.1 Transformer Interface Pins Transformer connections on the ICS1893BF signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8.4. The previous TP_CT pin on ...
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ICS1893BF Data Sheet Rev Release Note: Each of these pins monitor the data link by providing signals that directly drive LEDs. Table 8-5. PHY Address and LED Pins Pin Pin Pin Name Number Type P0AC 1 Input or ...
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ICS1893BF Data Sheet - Release Table 8-5. PHY Address and LED Pins Pin Pin Pin Name Number Type P2LI 4 Input or Output P3TD 6 Input or Output ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893BF Data Sheet Rev Release Table 8-5. PHY Address and LED Pins Pin Pin Pin Name Number Type P4RD 8 Input or Output ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description PHY (Address ...
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ICS1893BF Data Sheet - Release 8.2.3 Configuration Pins Table 8-6 lists the configuration pins. Table 8-6. Configuration Pins Pin Pin Name Number 10/100SEL 9 10TCSR 19 100TCSR 20 REF_IN 47 REF_OUT 46 RESETn 23 ICS1893BF, Rev. F, 5/13/10 Pin Type ...
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ICS1893BF Data Sheet Rev Release 8.2.4 MAC Interface Pins This section lists pin descriptions for each of the following interfaces • Section 8.2.4.1, “MAC Interface Pins for Media Independent Interface” 8.2.4.1 MAC Interface Pins for Media Independent Interface ...
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ICS1893BF Data Sheet - Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 26 Input/ Output RXCLK 34 Output ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893BF Data Sheet Rev Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXD0 31 Output RXD1 30 RXD2 29 RXD3 28 RXDV 32 Output RXER 35 Output TXCLK 37 ...
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ICS1893BF Data Sheet - Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXD0 39 Input TXD1 40 TXD2 41 TXD3 42 TXEN 38 Input ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin ...
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ICS1893BF Data Sheet Rev Release 8.2.5 Ground and Power Pins Table 8-8. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS ICS1893BF, Rev. F, 5/13/10 Chapter ...
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ICS1893BF Data Sheet - Release 8.3 ICS1893BK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) 10/100 1 AMDIX_EN 2 VSS 3 TP_AP 4 TP_AN 5 VDD 6 VDD 7 TP_BN 8 TP_BP 9 VSS 10 VDD_A 11 10TCSR 12 100TCSR ...
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ICS1893BF Data Sheet Rev Release 8.3.1 ICS1893BK Pin Descriptions The ICS1893BK Pin Signal Descriptions are identical in function to the ICS1893BF except for the Pin Numbers. See section 8.1 for descriptions. Table 8-9. ICS1893BK MAC Interface Pins Signal ...
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ICS1893BF Data Sheet - Release Table 8-11. ICS1893BK Configuration Pins Signal Name REF_IN REF_OUT RESETn 8.3.2 Transformer Interface Pins Transformer connections on the ICS1893BK signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8-12. The previous TP_CT pin used ...
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ICS1893BF Data Sheet Rev Release 8.3.3 Ground and Power Pins Table 8-13. ICS1893BK Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...
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ICS1893BF Data Sheet - Release Chapter 9 DC and AC Operating Conditions 9.1 Absolute Maximum Ratings Table 9-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893BF. These ratings, which are standard values for IDT commercially ...
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ICS1893BF Data Sheet Rev Release 9.3 Recommended Component Values Table 9-3. Recommended Component Values for ICS1893BF Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that drive ...
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ICS1893BF Data Sheet - Release 9.4 DC Operating Characteristics This section lists the ICS1893BF DC operating characteristics. 9.4.1 DC Operating Characteristics for Supply Current Table 9-4 lists the DC operating characteristics for the supply current to the ICS1893BF under various ...
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ICS1893BF Data Sheet Rev Release 9.4.3 DC Operating Characteristics for REF_IN Table 9-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 9-6. 3.3-V DC Operating Characteristics ...
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ICS1893BF Data Sheet - Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. ...
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ICS1893BF Data Sheet Rev Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for ...
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ICS1893BF Data Sheet - Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for the time ...
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ICS1893BF Data Sheet Rev Release 9.5.4 100M MII: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: ...
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ICS1893BF Data Sheet - Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • ...
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ICS1893BF Data Sheet Rev Release 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals ...
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ICS1893BF Data Sheet - Release 9.5.7 MII Management Interface Timing Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 9-14. MII Management Interface ...
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ICS1893BF Data Sheet Rev Release 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX ...
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ICS1893BF Data Sheet - Release 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • ...
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ICS1893BF Data Sheet Rev Release 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals ...
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ICS1893BF Data Sheet - Release 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893BF Data Sheet Rev Release 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the ...
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ICS1893BF Data Sheet - Release 9.5.13 100M MII Media Independent Interface: Receive Latency Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the ...
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ICS1893BF Data Sheet Rev Release 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet - Release 9.5.15 Reset: Power-On Reset Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-16 shows the ...
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ICS1893BF Data Sheet Rev Release 9.5.16 Reset: Hardware Reset and Power-Down Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet - Release 9.5.17 10Base-T: Heartbeat Timing (SQE) Table 9-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet Rev Release 9.5.18 10Base-T: Jabber Timing Table 9-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, ...
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ICS1893BF Data Sheet - Release 9.5.19 10Base-T: Normal Link Pulse Timing Table 9-26 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-26. 10Base-T Normal Link Pulse ...
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ICS1893BF Data Sheet Rev Release 9.5.20 Auto-Negotiation Fast Link Pulse Timing Table 9-27 lists the significant time periods for the ICS1893BF Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet - Release Chapter 10 Physical Dimensions of ICS1893BF Package Figure 10-1. ICS1893BF 300 mil SSOP Physical Dimensions ICS1893BF, Rev. F, 5/13/10 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 130 May, ...
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ICS1893BF Data Sheet Rev Release Figure 10-2. ICS1893BK Thermally Enhanced, Very Thin, Fine Pitch, Quad Flat / No Lead Plastic Package ICS1893BF, Rev. F, 5/13/10 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights ...
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... ICS1893BF Data Sheet - Release Chapter 11 Ordering Information Figure 11-1. shows ordering information for the ICS1893BF. Part / Order Number ICS1893BFLF 1893BFLF ICS1893BFLFT 1893BFLF ICS1893BFILF 1893BFILF ICS1893BFILFT 1893BFILF ICS1893BKLF 1893BKLF ICS1893BKLFT 1893BKLF ICS1893BKILF 1893BKILF ICS1893BKILFT 1893BKILF 11.1 Marking Diagram Notes: 1. Line 3: ###### = Lot number. ...
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ICS1893BF Data Sheet Rev Release Integrated Device Technology, Inc. Web Site: ICS1893BF, Rev. F, 5/13/10 http://www.idt.com Copyright © 2009, IDT, Inc. All rights reserved. 133 Chapter 11 Ordering Information May, 2010 ...