KSZ8721BL Micrel Inc, KSZ8721BL Datasheet

IC TXRX PHY 10/100 3.3V 48-LQFP

KSZ8721BL

Manufacturer Part Number
KSZ8721BL
Description
IC TXRX PHY 10/100 3.3V 48-LQFP
Manufacturer
Micrel Inc
Type
Transceiverr
Datasheets

Specifications of KSZ8721BL

Number Of Drivers/receivers
1/1
Protocol
MII, RMII
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
48-LQFP
Data Rate
100Mbps
No. Of Ports
1
Ethernet Type
IEEE 802.3u
Supply Current
151mA
Supply Voltage Range
3.3V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
LQFP
No. Of Pins
48
Interface Type
MII, RMII
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1627 - BOARD EVALUATION FOR KSZ8721BMC576-1626 - BOARD EVALUATION FOR KSZ8721BL
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1028-5
576-1511-5
576-1511-5
KSZ8721BL

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0
General Description
Operating with a 2.5V core to meet low-voltage and low-
power requirements, the KS8721BL and KS8721SL are
10BASE-T/100BASE-TX/FX Physical Layer Transceivers
that use MII and RMII interfaces to transmit and receive data.
They contain 10BASE-T Physical Medium Attachment (PMA),
Physical Medium Dependent (PMD), and Physical Coding
Sub-layer (PCS) functions. The KS8721BL/SL also have on-
chip 10BASE-T output filtering. This eliminates the need for
external filters and allows a single set of line magnetics to be
used to meet requirements for both 100BASE-TX and
10BASE-T.
The KS8721BL/SL automatically configures itself for 100 or
10Mbps and full- or half-duplex operation, using an on-chip
auto-negotiation algorithm. It is the ideal physical layer
transceiver for 100BASE-TX/10BASE-T applications.
Functional Diagram
May 2004
KS8721BL/SL
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
TX+
TX-
RX+
RX-
XO
XI
Transmitter
PLL
10BASE-T
Wander Correction
Receiver
MLT3 Decoder
Adaptive EQ
NRZI/NRZ
Base Line
Shaper
10/100
Pulse
MLT3 Encoder
NRZ/NRZI
Negotiation
PWRDWN
Recovery
Down or
Saving
Power
Clock
Auto
1
Features
• Single chip 100BASE-TX/100BASE-FX/10BASE-T
• 2.5V CMOS design; 2.5/3.3V tolerance on I/O
• 3.3V single power supply with built-in voltage regulator;
• Fully compliant to IEEE 802.3u standard
• Supports MII and Reduced MII (RMII)
• Supports 10BASE-T, 100BASE-TX, and 100BASE-FX
• Supports power-down and power-saving modes
• Configurable through MII serial management ports or via
• Supports auto-negotiation and manual selection for
• On-chip, built-in, analog front-end filtering for both
3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver
physical layer solution
Power consumption <340mW (including output driver
current)
with Far_End_Fault Detection
external control pins
10/100Mbps speed and full-/half-duplex modes
100BASE-TX and 10BASE-T
Manchester Encoder
Manchester Decoder
4B/5B Decoder
4B/5B Encoder
Parallel/Serial
Parallel/Serial
Serial/Parallel
Serial/Parallel
Descrambler
Scrambler
KS8721BL/SL
Rev. 1.1
Controller
Registers
MII/RMII
Interface
Driver
LED
and
MDIO
TXD3
TXD2
TXD1
TXD0
TXER
TXEN
CRS
COL
MDC
RXD3
RXD2
RXD1
RXD0
LINK
COL
SPD
TXC
RXER
RXDV
RXC
FDX
M9999-051704
Micrel

Related parts for KSZ8721BL

KSZ8721BL Summary of contents

Page 1

KS8721BL/SL General Description Operating with a 2.5V core to meet low-voltage and low- power requirements, the KS8721BL and KS8721SL are 10BASE-T/100BASE-TX/FX Physical Layer Transceivers that use MII and RMII interfaces to transmit and receive data. They contain 10BASE-T Physical Medium ...

Page 2

... Ordering Information Part Number Temp. Range KS8721BL +70 C 48-Pin LQFP KS8721SL +70 C 48-Pin SSOP KS8721BLI – +85 C 48-Pin LQFP KS8721SLI – +85 C 48-Pin SSOP KSZ8721BL +70 C 48-Pin LQFP KSZ8721SL +70 C 48-Pin SSOP 2 Micrel Package Lead Finish Standard Standard Standard Standard Lead-Free ...

Page 3

KS8721BL/SL Revision History Revision Date Summary of Changes 0.90 1/12/04 Created. 1.0 3/06/04 Initial release. Change to new format. Add part-ordering information. Editorial changes on pin description, RMII, and media converter operation. Update circuit design, reset timing, thermal resistance, electrical ...

Page 4

KS8721BL/SL Table Of Contents Pin Description ............................................................................................................................................................ 6 Strapping Option ......................................................................................................................................................... 9 Pin Configuration ...................................................................................................................................................... 10 Introduction ........................................................................................................................................................... 11 100BASE-TX Transmit ........................................................................................................................................ 11 100BASE-TX Receive ......................................................................................................................................... 11 PLL Clock Synthesizer ......................................................................................................................................... 11 Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 11 10BASE-T Transmit ............................................................................................................................................. ...

Page 5

KS8721BL/SL Register Map (continued) Register 15h: RXER Counter ...................................................................................................................................... 21 Register 1bh: Interrupt Control/Status Register .......................................................................................................... 21 Register 1fh: 100BASE-TX PHY Controller ................................................................................................................ 21 Absolute Maximum Ratings ........................................................................................................................................ 23 Operating Ratings ........................................................................................................................................................ 23 Electrical Characteristics ............................................................................................................................................ 23 Timing Diagrams .......................................................................................................................................................... ...

Page 6

KS8721BL/SL Pin Description Pin Number Pin Name Type 1 MDIO I/O 2 MDC I 3 RXD3/ Ipd/O PHYAD 4 RXD2/ Ipd/O PHYAD2 5 RXD1/ Ipd/O PHYAD3 6 RXD0/ Ipd/O PHYAD4 7 VDDIO P 8 GND GND 9 RXDV/ Ipd/O CRSDV/ ...

Page 7

KS8721BL/SL Pin Number Pin Name Type 19 TXD2 Ipd 20 TXD3 Ipd 21 COL/RMII Ipd/O 22 CRS/ Ipd/O RMII_BTB 23 GND GND 24 VDDIO P 25 INT#/ Ipu/O PHYAD0 26 LED0/TEST Ipu/O 27 LED1/ Ipu/O SPD100/ nFEF 28 LED2/ Ipu/O ...

Page 8

KS8721BL/SL Pin Number Pin Name Type 31 VDDRX 32 RX- 33 RX+ 34 FXSD/FXEN Ipd/O 35 GND GND 36 GND GND 37 REXT 38 VDDRCV 39 GND GND 40 TX- 41 TX+ 42 VDDTX 43 GND GND 44 GND GND ...

Page 9

KS8721BL/SL (1) Strapping Options Pin Number Pin Name Type 6,5, PHYAD[4:1]/ Ipd/O 4,3 RXD[0:3] 25 PHYAD0/ Ipu/O INT# 9 PCS_LPBK/ Ipd/O RXDV 11 ISO/RXER Ipd/O 21 RMII/COL Ipd/O 22 RMII_BTB Ipd/O CRS 27 SPD100/ Ipu/O No FEF/ LED1 28 DUPLEX/ ...

Page 10

KS8721BL/SL Pin Configuration MDIO 1 MDC 2 R3D3/PHYAD1 3 RXD2/PHYAD2 4 RXD1/PHYAD3 5 RXD0/PHYAD4 6 VDDIO 7 GND 8 RXDV/PCS_LPBK 9 RXC 10 RXER/ISO 11 GND 12 VDDC 13 TXER 14 TXC/REF_CLK 15 TXEN 16 TXD0 17 TXD1 18 TXD2 ...

Page 11

KS8721BL/SL Introduction 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit nibbles into a 125MHz serial bit ...

Page 12

KS8721BL/SL partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either full- or half-duplex mode (please refer to “Auto-Negotiation”). Auto-negotiation is disabled in the FX mode. During auto-negotiation, the contents of Register 4, ...

Page 13

KS8721BL/SL asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same ...

Page 14

KS8721BL/SL to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK. Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When ...

Page 15

KS8721BL/SL Auto-Crossover (Auto-MDI/MDI-X) Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of pinouts for a 10/100 BASE-T crossover function cable is shown below. This feature eliminates the confusion in applications by ...

Page 16

KS8721BL/SL Power Management The KS8721BL/SL offers the following modes for power management: Power-Down Mode: • This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low. Power-Saving Mode: • This mode can be disabled by ...

Page 17

KS8721BL/SL Circuit Design Reference for Power Supply Micrel’s integrated built-in, voltage regulator technology and thoughtful implementation allows the user to save BOM cost on both existing and future designs with the use of the new KS8721BL/SL single supply, single port ...

Page 18

KS8721BL/SL Register Map Register No. Description 0h Basic Control Register 1h Basic Status Register 2h PHY Identifier I 3h PHY Identifier II 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register 6h Auto-Negotiation Expansion Register 7h Auto-Negotiation Next Page ...

Page 19

KS8721BL/SL Address Name 1.10:7 Reserved 1.6 No Preamble 1.5 Auto-Negotiation Complete 1.4 Remote Fault 1.3 Auto-Negotiation Ability 1.2 Link Status 1.1 Jabber Detect 1.0 Extended Capability Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Register 3h - PHY ...

Page 20

KS8721BL/SL Address Name 5.11:10 Pause 5.9 100 BASE-T4 5.8 100BASE-TX Full-Duplex 5.7 100BASE-TX 5.6 10BASE-T Full-Duplex 5.5 10BASE-T 5.4:0 Selector Field Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved 6.4 Parallel Detection Fault 6.3 Link Partner Next Page Able 6.2 Next ...

Page 21

KS8721BL/SL Address Name Register 15h - RXER Counter 15.15:0 RXER Counter Register 1bh - Interrupt Control/Status Register 1b.15 Jabber Interrupt Enable 1b.14 Receive Error Interrupt Enable 1b.13 Page Received Interrupt Enable 1b.12 Parallel Detect Fault Interrupt Enable 1b.11 Link Partner ...

Page 22

KS8721BL/SL Address Name 1f.6 Enable Pause (Flow-Control Result) 1f.5 PHY Isolate 1f.4:2 Operation Mode Indication [000] = Still in auto-negotiation. 1f.1 Enable SQE Test 1f.0 Disable Data Scrambling Note: 1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch ...

Page 23

KS8721BL/SL Absolute Maximum Ratings Storage Temperature (T ) ....................... – +150 C S Supply Referenced to GND ........................ –0.5V to +4.0V All Pins ........................................................ –0.5V to +4.0V Important: Please read the Notes at the bottom of the page. ...

Page 24

KS8721BL/SL Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Propagation Delay Jitters 10BASE-TX Receive R RX+/RX– Differential IN Input Resistance V Squelch Threshold SQ 10BASE-TX Transmit (measured differentially after ...

Page 25

KS8721BL/SL Timing Diagrams Symbol Parameter t TXD [3:0] Set-Up to TXC High SU1 t TXEN Set-Up to TXC High SU2 t TXD [3:0] Hold After TXC High HD1 t TXEN Hold After TXC High HD2 t TXEN High to CRS ...

Page 26

KS8721BL/SL TXC TXEN TXD[3:0], TXER CRS TX+/TX- Symbol Parameter t TXD [3:0] Set-Up to TXC High SU1 t TXEN Set-Up to TXC High SU2 t TXD [3:0] Hold After TXC High HD1 t TXER Hold After TXC High HD2 t ...

Page 27

KS8721BL/SL RX+/RX- CRS RXDV RXD[3:0] RXER RXC Symbol Parameter t RXC Period P t RXC Pulse Width WL t RXC Pulse Width WH t RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC SU t RXD [3:0], RXER, RXDV ...

Page 28

KS8721BL/SL TX+/TX- TX+/TX- Figure 7. Auto-Negotiation/Fast Link Pulse Timing Symbol Parameter t FLP Burst to FLP Burst BTB t FLP Burst Width FLPW t Clock/Data Pulse Width PW t Clock Pulse to Data Pulse CTD t Clock Pulse to Clock ...

Page 29

KS8721BL/SL MDC MDI O (Into Ch ip) MDI O (Out of Chip) Symbol Parameter t MDC Period P t MDIO Set-Up to MDC (MDIO as Input) MD1 t MDIO Hold After MDC (MDIO as Input) MD2 t MDC to MDIO ...

Page 30

KS8721BL/SL Supply Voltage RST_N Strap-In Value Symbol Parameter t Stable Supply Voltages to Reset High sr Reference Circuit for Strapping Option Configuration Figure 10 shows the reference circuit for strapping option pins. Figure 10. Reference Circuit, Strapping Option Pins M9999-051704 ...

Page 31

KS8721BL/SL Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristic Turns Ratio Open-Circuit ...

Page 32

KS8721BL/SL Package Information M9999-051704 48-Pin SSOP (SM) 32 Micrel May 2004 ...

Page 33

KS8721BL/SL MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for ...

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