ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet
ECOG1X5A5L
Specifications of ECOG1X5A5L
Related parts for ECOG1X5A5L
ECOG1X5A5L Summary of contents
Page 1
... FLASH and 24Kbytes of SRAM. Products are available in a variety of QFN and BGA packages with pin counts between 68 and 208 pins. Comprehensive Development and Evaluation Kits are available. All are fully supported by Cyan's free, class-leading, integrated development environment, CyanIDE, which includes automatic peripheral configuration and an unrestricted ANSI C Compiler. • ...
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... Version 1.17 eCOG1X Microcontroller Product Family eCOG1X Device Options Part number Flash size eCOG1X0A5L 512K eCOG1X1A5L 512K eCOG1X4A5L 512K eCOG1X5A5L 512K eCOG1X8A5L 512K eCOG1X9A5L 512K eCOG1X10B5L 512K eCOG1X14B5L 512K eCOG1X10Z5L 512K eCOG1X14Z5L 512K eCOG1X0A5H 512K eCOG1X1A5H 512K eCOG1X4A5H 512K eCOG1X5A5H 512K ...
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... The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69. 2 Pins labelled NC may be connected internally and must be left open-circuit. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 69 GND eCOG1X0A5 Pin Description ...
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... PortB_4 32 PortT_1 16 VDD 33 PortT_2 17 VPP 34 PortT_3 1 The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69. 4 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 69 GND eCOG1X1A5 Pin Description 35 VDD 36 PortE_0 37 PortE_1 38 PortE_2 39 PortE_3 ...
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... The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69. 2 Pins labelled NC may be connected internally and must be left open-circuit. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 69 GND eCOG1X4A5 Pin Description ...
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... PortB_4 32 USB_p 16 VDD 33 USBVDD 17 VPP 34 USB_n 1 The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69. 6 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 69 GND eCOG1X5A5 Pin Description 35 VDD 36 PortE_0 37 PortE_1 38 PortE_2 39 PortE_3 ...
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... The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69. 2 Pins labelled NC may be connected internally and must be left open-circuit. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 69 GND eCOG1X8A5 Description Pin ...
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... VDD 33 17 VPP 34 1 The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69. 8 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 69 GND eCOG1X9A5 Description Pin Description EMAC_CRS / PortB_5 35 VDD EMAC_TXEN / PortB_6 ...
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... PortL_1 17 PortL_2 PortL_3 18 EMAC_CLKT / PortB_0 19 EMAC_CLKR / PortB_1 20 EMAC_RXER / PortB_2 21 EMAC_RXDV / PortB_3 22 EMAC_COL / PortB_4 23 VDD 24 VPP 25 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 101 GND eCOG1X10B5 www.cyantechnology.com Version 1.17 75 nReset 74 PortJ_3 73 PortJ_2 72 PortJ_1 71 VDD 70 PortJ_0 69 PortD_3 68 PortD_2 ...
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... VDD 49 25 VPP 50 1 The 100QFN package has a large central body contact which forms the GND pad. This is listed as pin 101. 10 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Description Pin Description EMAC_CRS / PortB_5 51 VDD EMAC_TXEN / PortB_6 52 PortE_0 EMAC_TXER / PortB_7 ...
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... PortL_1 16 17 PortL_2 PortL_3 18 EMAC_CLKT / PortB_0 19 EMAC_CLKR / PortB_1 20 EMAC_RXER / PortB_2 21 EMAC_RXDV / PortB_3 22 EMAC_COL / PortB_4 23 24 VDD 25 VPP 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 101 GND eCOG1X14B5 www.cyantechnology.com Version 1.17 75 nReset 74 PortJ_3 73 PortJ_2 72 PortJ_1 71 VDD 70 PortJ_0 69 PortD_3 68 ...
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... VDD 49 25 VPP 50 1 The 100QFN package has a large central body contact which forms the GND pad. This is listed as pin 101. 12 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Description Pin Description EMAC_CRS / PortB_5 51 VDD EMAC_TXEN / PortB_6 52 PortE_0 EMAC_TXER / PortB_7 ...
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... B12 NC A13 PortN_7 B13 PortN_5 A14 PortN_4 B14 PortN_2 A15 PortN_1 B15 PortN_0 A16 nReset_in B16 PortJ_2 A17 PortJ_0 B17 PortD_3 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc eCOG1X10Z5 Pin Description EMAC_TXD1 / A_1 C3 High_XTAL_In C4 AVDD C5 ADC2_Vin7 C6 ADC2_Vin3 ...
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... GND R14 NC P15 PortT_2 R15 USBVDD P16 PortE_4 R16 PortE_0 P17 PortE_5 R17 PortE_3 1 Pins labelled NC may be connected internally and must be left open-circuit. 14 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Pin Description G1 PortK_3 G2 PortK_2 G3 PortP_0 G4 VDD G14 VDD G15 ...
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... B12 NC A13 PortN_7 B13 PortN_5 A14 PortN_4 B14 PortN_2 A15 PortN_1 B15 PortN_0 A16 nReset_in B16 PortJ_2 A17 PortJ_0 B17 PortD_3 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc eCOG1X14Z5 Pin Description EMAC_TXD1 / A_1 C3 High_XTAL_In C4 AVDD C5 ADC2_Vin7 C6 ADC2_Vin3 ...
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... R14 USB_p P15 PortT_2 R15 USBVDD P16 PortE_4 R16 PortE_0 P17 PortE_5 R17 PortE_3 1 Pins labelled NC may be connected internally and must be left open-circuit. 16 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Pin Description G1 PortK_3 G2 PortK_2 G3 PortP_0 G4 VDD G14 VDD G15 ...
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... Port N pins 0-7 PortP_0-7 Port P pins 0-7 PortQ_0-7 Port Q pins 0-7 PortR_0-7 Port R pins 0-7 PortS_0-7 Port S pins 0-7 PortT_0-3 Port T pins 0-3 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Table 12: Pin functions www.cyantechnology.com Version 1.17 I PWR PWR ...
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... Applications which use the analogue inputs or outputs with the internal reference voltage must have external decoupling capacitors connected to the Vref pin. The recommended decoupling on this pin is a 100nF ceramic capacitor in parallel with a 4.7µF tantalum or aluminium electrolytic capacitor. 18 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Table 12: Pin functions www.cyantechnology.com I/O ...
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... Address mode Immediate Direct Indexed X Indexed Y Address mode PC relative X relative Direct Indexed Y 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 24 Syntax Data address #arg arg @arg Contents of address (arg) @(arg,x) Contents of address (arg + X reg) @(arg,y) Contents of address (arg + Y reg) ...
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... Harvard architecture CPU. The MMU provides both code space translations for program code and data space translations for variables and constants. A single physical memory can be mapped into both code and data space. 20 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... Optional extra IRAM (16K to 20K bytes) 2 0x5000 to 0x5FFF Optional extra IRAM, also used for (20K to 24K bytes) USB endpoint data buffer 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Sector size A16 A15 A14 A13 (Kbytes ...
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... CyanIDE are registered trademarks of Cyan Holdings plc Source Reset vector at location 0x0. User must insert a branch instruction at this address. Debug exception Timer/counters, watchdog timer expired MMU: access to an unmapped address EMI: access to a chip select that is disabled Exception interrupt from timer/counter module Exception interrupt from VDD 3 ...
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... The eICE debug interface requires only a 10-pin header on the target system. A low cost USB eICE adaptor plugs into this header and connects to the host PC via USB. This adaptor is used by the CyanIDE software development tool, allowing single stepping at C source code level and inspection or modification of variables or memory, while running the application on the target system. ...
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... Unused peripherals can have their clock stopped altogether, reducing their supply current to a minimum. The following diagram shows the complete eCOG1X SSM clocking scheme. 24 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc . www.cyantechnology.com 16 . ...
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... Microcontroller Product Family Figure 1: Detailed eCOG1X clocking scheme 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 25 ...
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... When configured as timers, they count at their input clock frequencies, set by the SSM. Alternatively, when configured as counters, they count when a selected edge occurs on their external clock signal inputs. These timer/counters are therefore suitable for counting external events in a target system. 26 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... Power saving features to start the UART clock automatically when the receiver detects a start bit and to hold the clock active during transmission. • Operates independently of the CPU, allowing the CPU to be put to sleep while the DUART transmit or receive is still active. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1. interrupt 27 ...
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... Address matching and arbitration. • Supports multi-master and master/slave operations. • Automatic acknowledge generation. • 7 bit, 10 bit and broadcast addressing. 28 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc bidirectional, multi-drop, multi-master, two wire 2 C function supports 100 kbps operation only. www.cyantechnology.com 11 February 2010 ...
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... Allows custom serial protocols to be emulated. • 255 symbols per frame. • Automatic parity generation and checking. • Start bit edge detection. • Transmit and receive data interrupts. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 29 ...
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... MMP mode: • Selectable block size: 256 x 16-bit data 32-bit data. • Three control signals: chip select, read/write direction, and wait. • Configurable control signal senses. 30 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... WS clock frequency = SCLK frequency divided by number of data bits x 2 (stereo audio has two data values per sample). • Programmable clock and data signal polarities. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 2 S peripheral provides both master and www.cyantechnology.com Version 1.17 ...
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... In return-to-zero mode, the outputs are set at the start of each period and cleared at their transition match times. • Supports edge-aligned, centre-aligned and user-defined PWM operating schemes. • Guard time or dead time mode. 32 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... MMU. Access to these registers is possible only when the MMU has been configured to set the base address for these registers in data space, and the SSM has been configured to provide a suitable clock signal to the EMAC. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 33 ...
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... FIFO. The USB core is controlled through a set of memory mapped registers, located at an address defined by the MMU. The USB DMA channel is controlled through the eCOG1X internal peripheral registers. 34 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... USRB_RX_CLK_OUT B_1 USRB_TX_CLK_OUT B_2 USRB_DATA_OUT B_3 USRB_DATA0_IN B_4 USRB_DATA1_IN B_5 USRB_DATA2_IN B_6 USRB_RX_CLK_IN B_7 USRB_TX_CLK_IN 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 3 4 EMI_D0 SCA_CLK EMI_D1 SCA_RESET EMI_D2 SCA_PWR_EN EMI_D3 SCA_CARD_IN EMI_D4 SCA_DATA EMI_D5 LCD_COM0 EMI_D6 UART2A_TX ...
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... EMI_DS0_WS0_CAS port.sel1 D_0 IR_RX SPI_CS0 SPI_SCLK D_1 IR_TX SPI_CS1 SPI_MOSI D_2 UART_TX SPI_CS2 SPI_MISO D_3 UART_RX SPI_CS3 SPI_CS0 36 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 14 USB_OTG_VBUSVALID USB_OTG_AVALID USB_OTG_BVALID USB_OTG_SESSEND USB_OTG_IDDIG USB_OTG_IDPULLUP USB_OTG_DRVVBUS USB_OTG_CHRGVBUS I2C_SCL I2C_SCL IR_RX I2C_SDA I2C_SDA IR_TX ...
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... G_0 EMI_A12 EHI_D12 G_1 EMI_A13 EHI_D13 G_2 EMI_A14_DQML EHI_D14 G_3 EMI_A15_DQMH EHI_D15 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 3 4 LCD_SEG16 SCB_CLK LCD_SEG17 SCB_RESET LCD_SEG18 SCB_PWR_EN LCD_SEG19 SCB_CARD_IN LCD_SEG20 SCB_DATA LCD_SEG21 PWM1 LCD_SEG22 UART2B_TX ...
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... LCD_SEG2 K_3 LCD_COM3 LCD_SEG3 port.sel3 K_0 IR_RX SPI_SCLK K_1 IR_TX SPI_MOSI K_2 UART_TX SPI_MISO K_3 UART_RX SPI_CS0 38 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc EHI_WAIT I2C_SCL I2C_SCL EHI_A0 I2C_SDA I2C_SDA EHI_A1 UART_TX IR_RX EHI_A2 UART_RX IR_TX 3 I2C_SCL I2C_SDA UART_TX ...
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... M_0 USRA_RX_CLK_OUT M_1 USRA_TX_CLK_OUT M_2 USRA_DATA_OUT M_3 USRA_DATA0_IN M_4 USRA_DATA1_IN M_5 USRA_DATA2_IN M_6 USRA_RX_CLK_IN M_7 USRA_TX_CLK_IN 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 3 4 I2C_SCL I2C_SCL I2C_SDA I2C_SDA UART_TX IR_RX UART_RX IR_TX 7 SCA_DATA SCA_CARD_IN SCB_DATA SCB_CARD_IN 2 3 ...
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... PIOA_10 LCD_SEG10 Q_3 PIOA_11 LCD_SEG11 Q_4 PIOA_12 LCD_SEG12 Q_5 PIOA_13 LCD_SEG13 Q_6 PIOA_14 LCD_SEG14 Q_7 PIOA_15 LCD_SEG15 40 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 3 SPI_SCLK_OUT SPI_SCLK_IN SPI_CS0_OUT SPI_CS0_IN SPI_DATA_IN SPI_DATA_OUT I2C_SCL I2C_SDA 6 7 USRA_RX_CLK_OUT SC_CLK_EN USRA_TX_CLK_OUT SC_RESET USRA_DATA_OUT SC_PWR_EN ...
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... USRA_RX_CLK_OUT S_1 USRA_TX_CLK_OUT S_2 USRA_DATA_OUT S_3 USRA_DATA0_IN S_4 USRB_RX_CLK_OUT S_5 USRB_TX_CLK_OUT S_6 USRB_DATA_OUT S_7 USRB_DATA0_IN 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc 3 4 USRA_RX_CLK_OUT USRA_RX_CLK_OUT USRA_TX_CLK_OUT USRA_TX_CLK_OUT USRA_DATA_OUT USRA_DATA_OUT USRA_DATA0_IN USRA_DATA0_IN USRA_DATA1_IN USRB_RX_CLK_OUT USRA_DATA2_IN USRB_TX_CLK_OUT USRA_RX_CLK_IN USRB_DATA_OUT ...
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... I2S_ALT_CLK_IN UART_TX T_3 I2S_MCLK UART_RX port.sel5 T_0 CNT1_TRIG CAP1_TRIG T_1 CNT2_TRIG CAP2_TRIG T_2 PWM1 PWM1 T_3 PWM2 PWM2 42 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc I2C_SCL IR_RX ESPI_SCLK I2C_SDA IR_TX ESPI_MOSI IR_RX UART_TX ESPI_MISO IR_TX UART_RX ESPI_CS0 CNT1_TRIG CNT1_TRIG ...
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... DUART Peripheral Signals UART1A_TX UART1A UART1A_RX UART1B_TX UART1B UART1B_RX UART2A_TX UART2A UART2A_RX UART2B_TX UART2B UART2B_RX 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports N_0-7 P_0-7 M_0-7 Q_0-7 R_0-7 S_0-7 Ports A_0 C_0 E_0 L_0 A_1 C_1 E_1 ...
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... Signals SC_CLK_EN SC_RESET SC_PWR_EN SCI SC_CARD_IN SC_DATA SC_DATA_IN SC_DATA_OUT Infra Red (IFR) Peripheral Signals IR_IN IR IR_OUT 44 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports C_2 D_2 F_2 J_2 K_2 C_3 D_3 F_3 J_3 K_3 Ports B_0 C_0 D_0 K_0 ...
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... CNT1 CNT1_TRIG CNT2 CNT2_TRIG PWM1 PWM1 PWM2 PWM2 Peripheral Signals CAP_TRIG1 CAP_TRIG1-2 CAP CAP_TRIG1-4 CAP_TRIG1-6 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports A_0 B_0 E_0 A_1 B_1 E_1 A_2 B_2 E_2 A_3 B_3 E_3 A_4 E_4 ...
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... The EHI peripheral is available only on eCOG1X devices in the 208BGA package. Peripheral Signals EHI_D0-7 EHI_D8-11 EHI_D12-15 EHI_D16-23 EHI_D24-26 EHI_D27-31/A3-7 EHI EHI_REQ EHI_ACK EHI_RW EHI_CS EHI_WAIT EHI_A0-2 46 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports A_0-7 H_0-7 I_0-7 E_0-7 E_0-7 F_0-3 G_0-1 G_2 G_3 D_0 D_0 D_1 D_1 D_2 D_2 ...
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... Peripheral Signals EMAC_TXD0-3 EMAC_RXD0-3 EMAC_CLKT EMAC_CLKR EMAC_RXER EMAC EMAC_RXDV EMAC_COL EMAC_CRS EMAC_TXEN EMAC_TXER 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports B_0 C_0 B_1 C_1 B_2 D_0 B_3 C_2 D_1 B_4 B_5 B_6 C_3 ...
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... COM0-3 SEG8-15 B_0-7 COM0 B_0 SEG9-15 B_1-7 COM0-3 B_0-3 SEG12-15 B_4-7 SEG16-23 SEG24-27 SEG24-31 COM0-3 SEG28-31 48 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports B_0 E_0 T_0 B_1 E_1 T_1 B_2 E_2 T_2 B_3 E_3 T_3 B_4 E_4 B_5 ...
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... ADC1_Vin4 ADC1_Vin5 ADC1_Vin6 ADC1_Vin7 ADC2_Vin1 ADC2_Vin2 ADC2_Vin3 ADC2 ADC2_Vin4 ADC2_Vin5 ADC2_Vin6 ADC2_Vin7 DAC1 DAC DAC2 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Ports B_0-5 E_0-5 R_0-5 C_0-2 Ports A_0 E_0 K_0 A_1 E_1 K_1 A_2 E_2 K_2 ...
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... The nReset_Out output is open-drain with an internal pull-up resistor, and can be used in a wired-OR connection with an external power-on reset if the external device also has an active-low open-drain output. 50 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc eCOG1X High_Xtal_Out High_Xtal_In ...
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... The ULPI_CLK input should be pulled low or tied to GND if the ULPI high-speed USB connection is not used. • The nTest pin is not used in normal applications and should be connected to VDD, either directly or via a 100kΩ pull-up resistor. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc eCOG1X Vref 100n GND Figure 4: Vref decoupling ...
Page 52
... Usually these signals are brought to a connector or pin header. A 10-way boxed header is preferred, as this provides mechanical polarisation and is compatible with the Cyan USB eICE debug adaptor. Suggested connections for this 10-way header on an eCOG1X target system are shown in the diagram below ...
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... AVDD and AGND, and make sure that the decoupling capacitors are located as close as possible to these pins. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 53 ...
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... Voltage on any digital I/O pin V IN relative to GND AV Voltage on any analogue pin IN V ESD protection ESD 54 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Min –40 Relative to GND 1.65 Relative to GND 3.0 Relative to AGND 1.62 Relative to GND 3.3V pins – ...
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... Supply current ADC (including V ) REF DAC I Supply current AV DAC DD Power-On Reset I Supply current POR 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions CPU clock frequency 64MHz 48MHz 24MHz 16kHz, clock source = low osc. IV (1.8V (3.3V 8.33MHz 16.66MHz ...
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... PortC_0-3, PortD_0-3, PortE_0-7, PortF_0-3, PortG_0-3, PortH_0-7, PortI_0-7, PortJ_0-3, PortM_0-7. 5 The following input pins and bidirectional port pins have Schmitt trigger input circuits: eICE_CLK/JTCLK, eICE_MOSI/JTDI, nReset_In, nReset, ULPI_CLK. 56 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Min –0.3 2.0 ≤ V GND– ...
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... To meet the USB specification requirements for the output impedance (28 Ω Ω ), fit external 18 Ω resistors in 1 series with both the USB_p and USB_n data pins. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Min Relative to AGND –0.3 ...
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... The crystal oscillator circuits require external load capacitors connected from both ends of the quartz crystal to GND, as shown in Applications Information. The recommended load capacitor values are 10pF for the low reference oscillator and 22pF for the high reference oscillator. 58 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions R not fitted EXT = 2.2M Ω ...
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... Clock fall time F Table 27: AC characteristics - external clock source 90% 10 Figure 7: External clock source timing diagram 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Error < 1% Error < 1% Table 26: AC characteristics - PLLs Conditions Clock at 90 more DD Clock at 10 ...
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... VDD are present on these pins. 4 The following pins have 4mA output drive capability: PortC_0-3, PortD_0-3, PortE_0-7, PortF_0-3, PortG_0-3, PortH_0-7, PortI_0-7, PortJ_0-3, PortM_0-7. 60 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Peripheral sample clock period determined by peripheral clock and prescaler configuration ...
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... Delay time EMI_CLK rising edge to data outputs tristate DZ t Delay time EMI_CLK rising edge to control signal output CO Table 31: AC characteristics - EMI SDRAM mode 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Min Min 5.0 4.8 Min 5.7 www.cyantechnology.com Version 1 ...
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... Figure 8: EMI bus mode 8-bit read cycle timing diagram EMI_CLK EMI_DS1, EMI_A0..A23 EMI_D0..D7 EMI_CS0, CS1 EMI_WS0, EMI_DS0 EMI_RW EMI_WAIT Figure 9: EMI bus mode 8-bit write cycle timing diagram 62 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc DSR DWR WAIT t ...
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... EMI_A0..A15 t AV EMI_A16_D8..A23_D15 EMI_D0.. EMI_CS0, CS1 EMI_WS0, WS1 EMI_DS0, DS1 t CO EMI_RW EMI_WAIT Figure 11: EMI bus mode 16-bit write cycle timing diagram 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc HAH DSR DWR addr[15: data[15: data[7: ...
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... Version 1.17 eCOG1X Microcontroller Product Family Figure 12: EMI SDRAM mode read cycle timing diagram 64 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... Microcontroller Product Family Figure 13: EMI SDRAM mode write cycle timing diagram 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 65 ...
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... EHI_WAIT Figure 14: EHI MMP read cycle timing diagram EHI_CS EHI_RW t AS EHI_A0..A2/A7 address(n) EHI_D0..D16/D32 EHI_WAIT Figure 15: EHI MMP write cycle timing diagram 66 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc for the CPU clock period. CPU address(n+ data( ...
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... Figure 16: EHI DMA master read cycle timing diagram EHI_REQ t EHI_ACK EHI_D0..D16/D32 Figure 17: EHI DMA master write cycle timing diagram 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Definition fd.ehi.cfg.dma_ack_act_prd1 fd.ehi.cfg.dma_ack_act_prd2 Table 33: EHI clock symbols Continue next transfer (min) Pause next transfer (max ...
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... Symbol Description T DUSART peripheral input clock period CLK N DUSART sample period (0..255 DUSART serial clock active period (0..255 DUSART serial clock inactive period (0..255 Serial data bit time (master mode) BIT 68 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc data( ...
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... Figure 20: SPI timing diagram, master mode, clk_pha = 0 CSn output t CSA SCLK output clk_pol = 1 SCLK output clk_pol = 0 MOSI output MISO input Figure 21: SPI timing diagram, master mode, clk_pha = 1 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc clk_pha = 0 clk_pha = 1 clk_pha = 0 clk_pha = 1 clk_pha = 0 clk_pha = CKA CKI t R ...
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... Figure 22: SPI timing diagram, slave mode, clk_pha = 0 CSn input t CSA SCLK input clk_pol = 1 SCLK input clk_pol = MISO output MOSI input Figure 23: SPI timing diagram, slave mode, clk_pha = 1 70 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc t t CKW data lsb out data lsb ...
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... N ESPI last clock to chip select delay (0..65535 ESPI chip select inactive delay (0..65535 Serial data bit time (master mode) BIT 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Definition rg.espi.ph0_time rg.espi.ph1_time rg.espi.cs_clk_time rg.espi.clk_cs_time rg.espi.if_time T x ((N CLK Table 39: ESPI clock symbols www ...
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... Figure 24: ESPI timing diagram, master mode, cpha = 0 CSn output t CSA SCLK output cpol = 0 SCLK output cpol = 1 MOSI output MISO input Figure 25: ESPI timing diagram, master mode, cpha = 1 72 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc CKA CKI data lsb out t t ...
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... Figure 26: ESPI timing diagram, slave mode, cpha = 0 CSn input t CSA SCLK input cpol = 0 SCLK input cpol = MISO output MOSI input Figure 27: ESPI timing diagram, slave mode, cpha = 1 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc t t CKW data lsb out data lsb ...
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... CW WS output t CD SD_OUT output SD_IN input Figure 28: I2S master mode timing diagram 74 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Definition Set by SSM External input signal clk_sel = 00 T CLK clk_sel = 10 T ACLK fd.i2s.cfg2.div_ratio Table 42: I2S clock symbols mclk_en = 0 mclk_en = 1 ...
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... Hold time SCLK rising edge to data input invalid DH Table 44: AC characteristics - I2S slave mode SCLK input WS input t CD SD_OUT output SD_IN input Figure 29: I2S slave mode timing diagram 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc CKL CKH www ...
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... Table 45: AC characteristics - I2S clock signals t ALT_CLK_IN input t 1 MCLK output SCLK output t 4 SCLK output Figure 30: I2S clock signals timing diagram 76 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc CKL CKH www.cyantechnology.com Min Typ Max ...
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... CLKR input t DS RXD[3:0], RXDV, RXER inputs 1 These are the limits for the transmit and receive input clock frequencies in order to meet the requirements of the IEEE802.3 standard. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions 10Mb 100Mb/s 10Mb ...
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... Delay time DIR input rising edge to data outputs tristate DZ t Delay time ULPI_CLK rising edge to data outputs enabled DE Table 48: AC characteristics - USB ULPI port ULPI_CLK input STP output NXT input DIR input DATA[7:0] DATA output 78 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions C = 600pF 90% of |(V – 50pF 90% of |(V – ...
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... DS DH eICE_MOSI cmd[31] cmd[30] eICE_MISO eICE_LOADB eICE_LOADB master eICE_LOADB slave t t CKH CKL eICE_CLK eICE_MOSI data[31] data[30] eICE_MISO 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc for the CPU clock period. CPU cmd[ Figure 33: eICE read timing diagram ...
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... The USB core is also fully static and has a minimum clock frequency of zero. However, in normal operation it requires a 48.0 MHz clock in order to meet the USB standard timing specifications. 80 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Clock frequency (MHz) Min ...
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... JTAG. If this function is not required, then the VPP pin should be connected to GND to minimise power consumption in normal operation. If this function is required, then connect VPP to GND via a pull-down resistor or jumper link so that the higher voltage programming supply can be connected. 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Min ...
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... Conversion time (software or timer triggered mode) Conversion rate (software or timer triggered mode) Temperature sensor sampling time Supply voltage sensor sampling time 82 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Enabled Disabled V stable REF Including V startup REF Sample/hold capacitor Conversion data valid ...
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... SNR Signal-to-noise ratio SFDR Spurious-free dynamic range THD Total harmonic distortion SINAD Signal-to-(Noise + Distortion) Noise floor ENOB Effective number of bits 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Excluding V error REF F = 50ks/s, –3dBFS 100ks/s, –3dBFS 200ks/s, –3dBFS ...
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... Applications which use the analogue inputs or outputs with the internal reference voltage must have external decoupling capacitors connected to the Vref pin. The recommended decoupling on this pin is a 100nF ceramic capacitor in parallel with a 4.7µF tantalum or aluminium electrolytic capacitor. 84 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Conditions Enabled Disabled ...
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... Microcontroller Product Family Figure 35: Vref variation with supply voltage (typical) Figure 36: Vref supply noise rejection versus frequency (typical) Figure 37: Voltage reference standby current with temperature (typical) 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 85 ...
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... Volts and T is the device temperature in °C. The ADC transfer function for single- OUT ended inputs is: where V is 1.22V nominally. To calculate the temperature from the ADC result value: REF where R is the ADC conversion result. 86 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc AV DD -------------- - V = OUT K ...
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... V V Threshold Voltage (Rising) TH Threshold Voltage (Falling) TH– DD Δ V Hysteresis Table 57: VDD low voltage sensor characteristics 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc Min 1.45 1.542 1.511 29 25 Min 2.729 2.668 www.cyantechnology.com Version 1.17 Typ Max Units 1 ...
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... Device family / architecture 1X Peripheral options 1 = ADC (subset) + DAC 2 = ADC + DAC 4 = USB 8 = Ethernet Ordering Information Part number Flash size eCOG1X0A5L 512K eCOG1X1A5L 512K eCOG1X4A5L 512K eCOG1X5A5L 512K eCOG1X8A5L 512K eCOG1X9A5L 512K eCOG1X10B5L 512K eCOG1X14B5L 512K eCOG1X10Z5L 512K eCOG1X14Z5L 512K eCOG1X0A5H 512K eCOG1X1A5H ...
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... Microcontroller Product Family Mechanical Package Drawings 68QFN 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 89 ...
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... Version 1.17 eCOG1X Microcontroller Product Family 100QFN 90 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... Microcontroller Product Family 208BGA 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 91 ...
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... Version 1.17 eCOG1X Microcontroller Product Family Circuit Board Pad Layout Drawings 68QFN 92 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... Microcontroller Product Family 100QFN 11 February 2010 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com Version 1.17 93 ...
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... Version 1.17 eCOG1X Microcontroller Product Family 208BGA 94 eCOG and CyanIDE are registered trademarks of Cyan Holdings plc www.cyantechnology.com 11 February 2010 ...
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... Cyan specifically disclaims any express or implied warranty of fitness for any or all of such uses. I2C and the I2C interface are patented by Philips Semiconductor in certain territories. ...