MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 119

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

M68HC11K Family
MOTOROLA
Many interrupt sources set associated flag bits when interrupts occur.
These flags are usually cleared during the course of normal interrupt
service. For example, the normal response to an RDRF interrupt request
in the SCI is to read the SCI status register to check for receive errors,
then read the received data from the SCI data register. It is precisely
these two steps which clear RDRF, so no extra steps are required.
An interrupt can be recognized at any time after it is enabled by its local
mask, if any, and by the global mask bit in the CCR. The CPU responds
to an interrupt at the completion of the instruction being executed. Since
the number of clock cycles in the instruction varies, so does interrupt
latency. The CPU pushes the contents of its registers onto the stack in
the order shown in
set (and the X bit as well if XIRQ is pending) to inhibit further interrupts.
The CPU fetches the interrupt vector for the highest priority pending
source, and execution continues at the address specified by the vector.
The interrupt service routine ends with the return-from-interrupt (RTI)
instruction, which tells the CPU to pull the saved registers from the stack
in reverse order so that normal program execution can resume.
Table 5-6. Stacking Order on Entry to Interrupts
Memory Location
Resets and Interrupts
Table
SP – 1
SP – 3
SP – 4
SP – 5
SP – 6
SP – 7
SP – 8
SP –2
SP
5-6. After the CCR value is stacked, the I bit is
CPU Registers
ACCA
ACCB
CCR
PCH
PCL
IYH
IXH
IYL
IXL
Resets and Interrupts
Technical Data
Interrupts
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