MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 174

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MC68HC711KS2MFN4

Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet

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Serial Peripheral Interface (SPI)
8.6.1 Serial Peripheral Control Register
Technical Data
174
NOTE:
Address: $0028
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
SPIE — Serial Peripheral Interrupt Enable Bit
SPE — Serial Peripheral System Enable Bit
DWOM — Port D Wired-OR Mode Bit
MSTR — Master Mode Select Bit
Reset:
Read:
Write:
DWOM affects only the four SPI pins on port D, PD[5:2]. See also
7.9.2 Serial Communications Control Register 1
of the WOMS (wired-OR Mode for SCI pins) bit in the serial
communications control register 1 (SCCR1).
0 = SPI interrupt disabled
1 = SPI interrupt is enabled each time the SPIF or MODF status
0 = SPI off
1 = SPI on — PD[5:2] function as SPI signals
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
Figure 8-3. Serial Peripheral Control Register (SPCR)
U = Undefined
SPIE
Bit 7
flag in SPSR is set.
0
Serial Peripheral Interface (SPI)
SPE
6
0
DWOM
5
0
MSTR
4
0
CPOL
3
0
CPHA
2
1
for a discussion
M68HC11K Family
SPR1
U
1
MOTOROLA
SPR2
Bit 0
U

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