MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 179

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

8.6.5 System Configuration Options 2
M68HC11K Family
MOTOROLA
Address: $0038
1. Not available on M68HC11K devices
LSBF — Least Significant Bit First Enable Bit
SPR2 — SPI Clock Rate Select Bit
Reset:
Read:
Write:
Figure 8-7. System Configuration Options 2 Register (OPT2)
Setting LSBF causes data to be transmitted LSB first (the default is
MSB first). LSBF does not affect bit positions in the data register;
reads and writes always have MSB in bit 7.
SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the
two bits in the SPCR, this specifies the SPI clock rate. See
LIRDV
Bit 7
0
Serial Peripheral Interface (SPI)
CWOM
6
0
STRCH
5
0
(1)
IRVNE
—
4
LSBF
3
0
Serial Peripheral Interface (SPI)
SPR2
2
0
XDV1
1
0
Technical Data
SPI Registers
Table
XDV0
Bit 0
0
8-1.
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