MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 205

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MC68HC711KS2MFN4

Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet

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9.7.1 Port A Data Direction Register
9.7.2 Pulse Accumulator Control Register
M68HC11K Family
MOTOROLA
NOTE:
Address: $0001
Address: $0026
The pulse accumulator uses port A, bit 7 as the PAI input, but the pin can
also be used as general-purpose I/O or as an output compare.
Even when port A, bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
DDA7 — Data Direction Control for Port A, Bit 7
PAEN — Pulse Accumulator System Enable Bit
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 9-23. Pulse Accumulator Control Register (PACTL)
0 = PA7 configured as an input
1 = PA7 configured as an output
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
Figure 9-22. Port A Data Direction Register (DDRA)
DDA7
Bit 7
Bit 7
0
0
0
DDA6
PAEN
Timing System
6
0
6
0
PAMOD
DDA5
5
0
5
0
PEDGE
DDA4
4
0
4
0
DDA3
3
0
3
0
0
DDA2
I4/O5
2
0
2
0
Pulse Accumulator (PA)
DDA1
RTR1
1
0
1
0
Timing System
Technical Data
DDA0
RTR0
Bit 0
Bit 0
0
0
205

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