MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 40

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

Pin Description
Technical Data
40
Address: $0038
In single-chip and bootstrap modes, the MODA pin typically is grounded
and has no function after reset. In expanded and special test modes,
MODA is normally connected to V
and functions as the load instruction register (LIR) pin after reset. The
open-drain, active-low LIR output drives low during the first E-clock cycle
of each instruction (opcode fetch), providing a useful signal for system
debugging.
LIR can be driven high for a portion of each instruction cycle by setting
the LIRDV bit in the system configuration options 2 (OPT2) register (see
Figure 2-7
instructions and prevent false triggering in high-speed applications.
LIRDV — LIR Driven Bit
Reset:
Read:
Write:
PREVIOUS INSTRUCTION
0 = LIR not driven high
1 = LIR driven high for one quarter cycle to reduce transition time
1. STRCH is not available on K devices.
Figure 2-7. System Configuration Options 2 (OPT2)
LIRDV
LAST CYCLE OF
Bit 7
0
LIR
E
and
CWOM
Figure
Pin Description
6
0
STRCH
2-8). This feature can help detect consecutive
FIRST CYCLE OF NEW
INSTRUCTION
Figure 2-8. LIR Timing
5
0
(1)
OPCODE FETCH
IRVNE
Note: If LIRDV is not set, the pullup resistor may
—
DD
4
through a 4.7-k pullup resistor
not return the level to a logic 1 before
the next data fetch.
LSBF
3
0
SPR2
2
0
M68HC11K Family
XDV1
1
0
MOTOROLA
XDV0
Bit 0
0