MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 53

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

3.5 Opcodes and Operands
3.6 Addressing Modes
M68HC11K Family
MOTOROLA
there are no special requirements for alignment of instructions or
operands.
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Every
instruction requires a unique opcode for each of its addressing modes.
The resulting number of opcodes exceeds the 256 available in an 8-bit
binary number. A 4-page opcode map has been implemented to
accommodate the extra instructions. An additional byte, called a
prebyte, directs the processor from page 0 of the opcode map to one of
the other three pages. As its name implies, the additional byte precedes
the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero
to three operands. The operands contain information the CPU needs for
executing the instruction. Complete instructions can be from one to five
bytes long.
Six addressing modes can be used to access memory:
All modes except inherent mode use an effective address. The effective
address is the memory address where the argument is fetched or stored
or the address from which execution is to proceed. The effective address
can be specified within an instruction or it can be calculated.
1. Immediate
2. Direct
3. Extended
4. Indexed
5. Inherent
6. Relative
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcodes and Operands
Technical Data
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