MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 57

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MC68HC711KS2MFN4

Manufacturer Part Number

MC68HC711KS2MFN4

Description

32K EPROM - SLOW MODE

Manufacturer

Freescale Semiconductor

Datasheet

1.MC68HC711KS2MFN4.pdf (290 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

MC68HC711KS2MFN4

Manufacturer:

Freescale

Quantity:

300

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M68HC11K Family

MOTOROLA

BRCLR(opr)

BRSET(opr)

BSET (opr)

CMPA (opr)

CMPB (opr)

Mnemonic

BITA (opr)

BITB (opr)

CLR (opr)

BEQ (rel)

BGE (rel)

BGT (rel)

BHS (rel)

BNE (rel)

BRA (rel)

BRN (rel)

BSR (rel)

BVC (rel)

BLE (rel)

BLO (rel)

BLS (rel)

BPL (rel)

BVS (rel)

BLT (rel)

BMI (rel)

BHI (rel)

CLRA

CLRB

CBA

CLC

CLV

CLI

(msk)

(rel)

(msk)

(rel)

(msk)

Branch if = Zero

Branch if

Branch if > Zero

Higher or Same

Branch if

Branch if Lower

Branch if Lower

Branch if < Zero

Compare A to B

Branch if Minus

Branch Always

Overflow Clear

Clear Overflow

Branch if not =

Branch if Bit(s)

Clear Carry Bit

Accumulator A

Accumulator B

Clear Interrupt

Clear Memory

Branch if Plus

Branch Never

Compare A to

Compare B to

with Memory

with Memory

Overflow Set

Bit(s) Test A

Bit(s) Test B

Subroutine

Operation

Bit(s) Clear

Branch to

Set Bit(s)

Branch if

Branch if

Branch if

Branch if

Branch if

or Same

Memory

Memory

Higher

Mask

Clear

Clear

Zero

Byte

Flag

Set

Zero

Zero

? Z + (N

? Z + (N

See

? (M) • mm = 0

? M • mm = 0

M + mm

Description

? N

? N

? C + Z = 0

? C + Z = 1

? Z = 1

? C = 0

? C = 1

? N = 1

? Z = 0

? N = 0

? V = 0

? V = 1

? 1 = 1

? 1 = 0

0

Figure 3-2

0

0

0

0

A – M

B – M

A • M

B • M

A – B

0

Table 3-1. Instruction Set (Sheet 2 of 7)

V = 0

V = 1

C

M

A

B

V

I

V) = 0

V) = 1

M

A

A

A

A

A

B

B

B

B

B

A

B

A

A

A

A

A

B

B

B

B

B

Central Processor Unit (CPU)

Addressing

Mode

REL

REL

REL

REL

REL

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

REL

REL

REL

REL

REL

REL

REL

REL

DIR

IND,X

IND,Y

REL

DIR

IND,X

IND,Y

DIR

IND,X

IND,Y

REL

REL

REL

INH

INH

INH

EXT

IND,X

IND,Y

INH

INH

INH

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

18

18

18

18

18

18

18

18

Opcode

27

2C

2E

22

24

85

95

A5

A5

C5

D5

E5

E5

2F

25

23

2D

2B

26

2A

20

13

1F

1F

21

12

1E

1E

14

1C

1C

8D

28

29

11

0C

0E

7F

6F

6F

4F

5F

0A

81

91

A1

A1

C1

D1

E1

E1

B5

F5

B1

F1

Instruction

rr

rr

rr

rr

rr

ii

dd

hh ll

ff

ff

ii

dd

hh ll

ff

ff

rr

rr

rr

rr

rr

rr

rr

rr

dd mm rr

ff mm rr

ff mm rr

rr

dd mm rr

ff mm rr

ff mm rr

dd mm

ff mm

ff mm

rr

rr

rr

hh ll

ff

ff

ii

dd

hh ll

ff

ff

ii

dd

hh ll

ff

ff

Operand

—

—

—

—

—

—

Cycles

3

3

3

3

3

2

3

4

4

5

2

3

4

4

5

3

3

3

3

3

3

3

3

6

7

8

3

6

7

8

6

7

8

6

3

3

2

2

2

6

6

7

2

2

2

2

3

4

4

5

2

3

4

4

5

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

S

Central Processor Unit (CPU)

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

X

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

H

Condition Codes

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

0

I

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

N

0

0

0

Technical Data

Instruction Set

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Z

1

1

1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

V

0

0

0

0

0

0

0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

C

0

0

0

0

57

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