ICE2PCS05 Infineon Technologies, ICE2PCS05 Datasheet - Page 11

• Manufacturer Part Number: ICE2PCS05
• Description: Power Factor Correction ICs Standalone PFC CTRLR IN CCM
• Manufacturer: Infineon Technologies

Specifications of ICE2PCS05

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: ICE2PCS05XK

voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
3.7
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T
are designed to meet a maximum duty cycle D
95% at the GATE output under 136kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 14.
Figure 14
3.8
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
sensing voltage at VSENSE which is a resistive divider
tapping from V
OTA1 which has an internal reference of 3V. Figure 15
shows the important blocks of this voltage loop.
3.8.1
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 15). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
Version 1.0
PWM on signal
Current Loop
Peak Current
2.5% of T
Toffmin
PWM Logic
Voltage Loop
OUT
Voltage Loop Compensation
Limit
PWM Logic
. This loop is closed by the feedback
OUT
. The pin VSENSE is the input of
Limit Latch
Current
PWM on
S
R
Latch
R
S
L1
L2
Q
Q
G1
turn GATE on
HIGH =
OFFMIN
MAX
of
,
11
Figure 15
3.8.2
Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a “window detector” for the
feedback voltage V
Whenever V
by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of V
3.9
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 16) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold V
drive is internally pull low to maintain the off state.
Full-wave
Retifier
Av(I
From
V
IN
IN
)
PWM Generation
Current Loop
Output Gate Driver
Enhanced Dynamic Response
Voltage Loop
VSENSE
R7
L1
OUT
+
.
Nonlinear
t
Gain
exceeds the reference value (3V)
VSENSE
Functional Description
C4
R6
D1
Gate Driver
VCOMP
at pin 6 (VSENSE).
OTA1
ICE2PCS05/G
C2
C5
3V
CCUVLO
CCM-PFC
R3
R4
09 Oct 2008
VSENSE
GATE
Vout
, the gate