Supervisory Circuits 16K I2C Mem w/Reset

 

CAT1162PI-45

Manufacturer Part NumberCAT1162PI-45
DescriptionSupervisory Circuits 16K I2C Mem w/Reset
ManufacturerCatalyst / ON Semiconductor
CAT1162PI-45 datasheets

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Specifications of CAT1162PI-45

Number Of Voltages Monitored1Monitored Voltage3 V, 3.3 V, 5 V
Output TypeActive High, Active Low, Open DrainManual ResetResettable
WatchdogNo WatchdogBattery Backup SwitchingNo Backup
Supply Voltage (max)6 VSupply Voltage (min)2.7 V
Supply Current (typ)3000 uAMaximum Power Dissipation1000 mW
Maximum Operating Temperature+ 85 CMounting StyleThrough Hole
Package / CasePDIP-8Minimum Operating Temperature- 40 C
Power Fail DetectionNoLead Free Status / Rohs StatusLead free / RoHS Compliant
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Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1161/2 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the CAT1161/2 is still busy with the write operation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to
protect against inadvertent memory array program-
ming. If the WP pin is tied to V
, the entire memory
CC
array is protected and becomes read only. The
CAT1161/2 will accept both slave and byte
addresses, but the memory location accessed is
protected from programming by the device’s failure
to send an acknowledge after the first byte of data is
received.
Figure 9. Immediate Address Read Timing
BUS ACTIVIT Y:
MASTER
SDA LINE
SCL
SDA
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
READ OPERATIONS
The READ operation for the CAT1161/2 is initiated in the
same manner as the write operation with one exception,
that R/W ¯ ¯ bit is set to one. Three different READ ope–
rations are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT1161/2 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N+1. For all devices,
N=E=2047. The counter will wrap around to Zero and
continue to clock out valid data for the 16K devices.
After the CAT1161/2 receives its slave address
information (with the R/W ¯ ¯ bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.
S
T
A
SLAVE
R
ADDRESS
T
S
A
DATA
C
K
8
9
8TH BI T
DATA OUT
NO ACK
9
CAT1161, CAT1162
S
T
O
P
P
N
O
A
C
K
STOP
Doc. No. MD-3002 Rev. I

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