ispPAC-POWR1014A-02TN48I Lattice, ispPAC-POWR1014A-02TN48I Datasheet

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... Supply POL#N ADC* 4 Timers ispPAC-POWR1014A *ispPAC-POWR1014A only. Description Lattice’s Power Manager II ispPAC-POWR1014 general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor power supply test points ...

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... The I C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V inputs, read back the status of each of the V control the output pins (ispPAC-POWR1014A only). The JTAG interface can be used to read out all I during manufacturing. Figure 2-1. ispPAC-POWR1014/A Block Diagram VMON1 ...

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... Open Drain Output 2 OUT13 Open Drain Output 1 OUT14 Open Drain Output 7 40 RESETb Digital I/O ispPAC-POWR1014/A Data Sheet Voltage Range 1, 2 VCCINP PLD Logic Input 1 Registered by MCLK 1, 3 VCCINP PLD Logic Input 2 Registered by MCLK 1, 3 VCCINP PLD Logic Input 3 Registered by MCLK ...

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... VCCD and VCCA pins must be connected together on the circuit board. 6. Open-drain outputs require an external pull-up resistor to a supply. 7. The RESETb pin should only be used for cascading two or more ispPAC-POWR1014/A devices. 8. These pins should be connected to GNDD (ispPAC-POWR1014 only). 9. The VCCPROG pin MUST be left floating when V 10. SCL should be tied high and SDA is don’ ...

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... CCD CCA V and V not powered CCD CCA pins OUT[3:14] pins HVOUT[1:2] pins in open-drain mode Power applied ESD Stress Min. HBM 2000 CDM 1000 2-5 ispPAC-POWR1014/A Data Sheet Min. Max. -0.5 4.5 -0.5 4.5 -0.5 6 -0.5 6 -0.5 4 -0.5 6 -0.5 6 -0.5 13.3 -0.5 ...

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... Gate driver output voltage PP Gate driver source current  I OUTSRC (HIGH state) Gate driver sink current  I OUTSINK (LOW state) 1. 12V setting only available on ispPAC-POWR1014-02 and ispPAC-POWR1014A-02. Conditions During programming cycle supplies. Conditions 1 range, operating temperature, process. CCA Conditions 1 12V setting ...

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... Corresponds to VCCA and VCCD supply voltages. Conditions 2 Time from I C request Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 3 pin (theoretical maximum is 6.144V). Conditions Measurement Range 600 mV - 2.048V, Attenuator =1 Conditions 2-7 ispPAC-POWR1014/A Data Sheet Min. Typ. Max. 10 100 0 2.048 +/- 0.1 1 Min. Typ. Max. -8 ...

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... Lattice Semiconductor Figure 2-2. ispPAC-POWR1014/A Power-On Reset Reset State T BRO T T RST POR Start Up State T START Analog Calibration T GOOD 2-8 ispPAC-POWR1014/A Data Sheet VCC RESETb MCLK PLDCLK AGOOD (Internal) ...

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... Spacing between available Resolution adjacent timer intervals Accuracy Timer accuracy Over Recommended Operating Conditions Conditions f = 8MHz CLK f = 8MHz CLK f = 8MHz CLK 2-9 ispPAC-POWR1014/A Data Sheet Min. Typ. Max 7.6 8 8.4 7.2 8.8 250 0.032 1966 13 -6.67 -12.5 Units µ ...

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... TDI, TMS, ATDI, TDISEL, 3.3V supply TDI, TMS, ATDI, 1 TDISEL, 2.5V supply SCL, SDA IN[1: 10mA SINK I = 20mA SINK I = 4mA SINK I = 4mA SRC CCJ 2-10 ispPAC-POWR1014/A Data Sheet Min. Typ. Max. +/- 100 70 0.8 0.7 30% V CCD 30% V CCINP 2.0 1.7 70 CCD ...

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... T Device must be operational after power-on reset POR T Bus free time between stop and start condition BUF 1. Applies to ispPAC-POWR1014A only less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this case, waiting for the T ...

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... State Update-IR Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL PWP CKH Run-Test/Idle (Program) Select-DR Scan 2-12 ispPAC-POWR1014/A Data Sheet Min. Typ. Max. 10 — — 30 — — 30 — — 200 — — — — 10 — — — — 10 — — 20 — ...

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... Theory of Operation Analog Monitor Inputs The ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 2-7. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 370 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV ‘ ...

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... Lattice Semiconductor Figure 2-7. ispPAC-POWR1014/A Voltage Monitors VMONx Trip Point A Trip Point B Analog Input Figure 2-7 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. ...

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... To monitor under-voltage fault conditions, the LTP should be used. Tables 2-1 and 2-2 show both the under-voltage and over-voltage trip points, which are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. UTP LTP 2-15 ispPAC-POWR1014/A Data Sheet (a) (b) ...

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... Data Sheet 2.719 3.223 3.839 4.926 2.705 3.206 3.819 4.900 2.691 3.190 3.799 4.875 2.677 3.173 3.779 4.849 2.663 3 ...

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... Data Sheet 2.691 3.190 3.799 4.875 2.677 3.173 3.779 4.849 2.663 3.156 3.759 4.823 2.649 3.139 3.739 4.798 2.634 3 ...

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... The third section in the ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the compara- tor output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16µ ...

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... Lattice Semiconductor VMON Voltage Measurement with the On-chip Analog to Digital Converter  (ADC, ispPAC-POWR1014A Only) The ispPAC-POWR1014A has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. Figure 2-9. ADC Monitoring VMON1 to VMON10 VMON1 VMON2 VMON3 ...

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... GLB1, GLB2, and GLB3. Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the ispPAC-POWR1014/A device. The output signals of the ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 2-10. GLB3 generates timer control ...

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... Polarity Clock Clock and Timer Functions Figure 2-12 shows a block diagram of the ispPAC-POWR1014/A’s internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 2-12. Clock and Timer System Internal ...

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... In addition to being usable as digital open-drain outputs, the ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output pins can be programmed to operate as high-voltage FET drivers. Figure 2-14 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the PLD, or with the ispPAC-POWR1014A, from the I isters (see Figure 2-14). For further details on controlling the outputs through I ...

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... VMONs, and ADCs will not be operational until 500 microseconds (max.) after the conclusion of the RESET event. I SOURCE 1 ) (12.5 to 100 µ SINK (100 to 500 µA) +Fast Turn-off (3000µ Register 1 . The maximum voltage levels that are required depend on the gate-to-source 2 C 2-23 ispPAC-POWR1014/A Data Sheet Input Supply HVOUTx Pin Load steps. ...

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... CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPAC- POWR1014/A device operation, results in the device aborting all operations and returning to the power-on reset state. The status of the power supplies which are being enabled by the ispPAC-POWR1014/A will be determined by the state of the outputs shown above. ...

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... The second transaction performs the actual read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPAC- POWR1014A asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ispPAC-POWR1014A ...

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... START DEVICE ADDRESS (7 BITS) The ispPAC-POWR1014A provides 17 registers that can be accessed through its I provide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and from the device. Table 2-7 provides a summary of these registers. ...

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... VMON_STATUS1 (Read Only) VMON8B VMON8A b7 0x02 - VMON_STATUS2 (Read Only also possible to directly read the value of the voltage present on any of the VMON inputs by using the ispPAC- POWR1014A’s ADC. Three registers provide the I 1 Description R VMON input status Vmon[4:1] R VMON input status Vmon[8:5] ...

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... C master load a second conversion command only after the completion of the current conversion ATTEN SEL3 Resolution 2mV 6mV Select Word SEL2 SEL1 (ADC_MUX.2) (ADC_MUX.1) (ADC_MUX. 2-28 ispPAC-POWR1014/A Data Sheet 1 1 DONE SEL2 SEL1 SEL0 Full-Scale Range 2.048 V 6.144 V SEL0 Input Channel 0 VMON1 1 VMON2 0 VMON3 1 VMON4 0 VMON5 1 VMON6 0 VMON7 1 VMON8 0 VMON9 1 VMON10 0 VCCA 1 VCCINP ...

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... ADC convert commands CONVERT PLD Output/Input_Value Register Select (E 2 Configuration) 3 MUX USERJTAG 2 Bit 3 MUX 3 3 Input_Value Input_Status Interface Unit IN4 2-29 ispPAC-POWR1014/A Data Sheet more than 50kHz and verify 2 C commands. Figure 2-20 PLD Array IN3 IN2 IN1 interface, as shown in Figure 2-21. The 2 C ...

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... OUT14 OUT13 OUT12 GP6 GP5 GP4 GP14 GP13 GP12 interface, with the register mapping shown in Figure 2-22. 2-30 ispPAC-POWR1014/A Data Sheet C bus instead of by the PLD array. The outputs 14 HVOUT[1..2] OUT[3..14] OUT3 HVOUT2 HVOUT1 OUT11 OUT10 OUT9 GP3_ENb GP2 GP1 b2 b1 ...

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... The I C interface also provides the ability to initiate reset operations. The ispPAC-POWR1014A may be reset by issuing a write of any value to the I is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I section of this data sheet for further information. ...

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... After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ispPAC-POWR1014A. As part of the service functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP3_ENb to re-enable the SMBAlert function ...

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... To meet such application needs, the ispPAC-POWR1014/A provides an alternate programming method which enables the programming of the ispPAC-POWR1014/A device through the JTAG chain with a sepa- rate power supply applied just to the programming section of the ispPAC-POWR1014/A device with the main power supply of the board turned off. ...

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... TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the ispPAC-POWR1014/A are connected to the header as shown in Figure 2-27. Note: The ispPAC-POWR1014/A should be the last device in the JTAG chain. ...

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... VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the ispPAC-POWR1014/A is powered by the VCCPROG pin, no power should be applied to the VCCD and VCCA pins. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOSFET driver are driven low, and all other inputs are ignored ...

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... PC with a Lattice ispDOWNLOAD™ cable. The board demon- strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro- cess. Input and output connections are provided to aid in the evaluation of the functionality implemented in ispPAC- POWR1014/A for a given application. (Figure 2-29). ...

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... E CMOS cells these non-volatile cells that store the configuration or the ispPAC-POWR1014/A. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibil- ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func- tionally specified, but inclusion is strictly optional ...

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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver- ...

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... BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC- POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). ...

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... TDI and TDO. Again, since the ispPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000). ...

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... OUTPUTS_HIGHZ. DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispPAC-POWR1014/A for a read cycle. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_ADDRESS – This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_DATA_SHIFT – ...

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... Accessing I C Registers through JTAG (ispPAC-POWR1014A Only registers can be read or written through the JTAG interface of the ispPAC-POWR1014A devices using the two JTAG command codes shown in Table 2-12. 2 Note: The SCL pin of the I C port should be pulled high during the entire time that the I accessed via the JTAG port ...

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... These bytes consist of the status of VMONxA and VMONxB comparators corresponding to VMON1 through VMON10 inputs. In the following tables, the number in the parenthesis indicates the bit position within the I2C_Data_Register Packet. During the I2C_Data_Register write operation, the contents of these bytes are ignored because the VMON status registers are read only. ispPAC-POWR1014/A Data Sheet ...

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... VMON10B 1 (53) (52) (51 Address = 0x07 (45) (44) (43 Address = 0x08 (37) (36) (35 Address = 0x09 SEL2 SEL3 ATTEN (29) (28) (27 (21) (20) (19) (18) 2-44 ispPAC-POWR1014/A Data Sheet 2 C Address = 0x00 VMON3B VMON4A VMON4B (66) (65) (64) VMON7B VMON8A VMON8B (58) (57) (56 (50) (49) (48 (42) (41) (40) D9 D10 D11 (34) (33) (32 (26) (25) (24) 2 ...

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... Byte 2 – GP_OUTPUT1 (Read Operation) – When I2C_Control_Register Bit 3 =0, Bit 2=0, I GP1 GP2 GP3_ENb (15) (14) (13) Byte 2 – OUTPUT_STATUS0 (Read Operation) – When I2C_Control_Register Bit 3 =0, Bit 2=1, I HVOUT1 HVOUT2 OUT3 (15) (14) (13) ispPAC-POWR1014/A Data Sheet (20) (19) (18) (17) IN4 (20) (19) (18) ...

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... JTAG Access Method Example This example shows various steps required to measure the voltage applied to the VMON5 of the ispPAC- POWR1014A device. These steps include transition through the TAP states shown in Figure 2-31. This example assumes that 5V is applied to VMON5. Figure 2-42. VMON5 JTAG Access Example TRST ON ...

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... Input_value 1. “X” = Non-functional bit (bits read out as 1's).  “-“ = State depends on device configuration of input status. ispPAC-POWR1014/A Data Sheet Read/Write Description R VMON input status Vmon[1:4] R VMON input status Vmon[5:8] R VMON input status Vmon[9:10] Output status HVOUT[1:2], ...

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... A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. 0. SEATING PLANE 0.08 C LEAD FINISH BASE METAL 2-48 ispPAC-POWR1014/A Data Sheet 0. 0.20 MIN. A1 1.00 REF. DETAIL "A" SYMBOL MIN ...

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... A = ADC present ispPAC-POWR1014/A Ordering Information Conventional Packaging Part Number ispPAC-POWR1014A-01T48I ispPAC-POWR1014-01T48I ispPAC-POWR1014A-02T48I ispPAC-POWR1014-02T48I Lead-Free Packaging Part Number ispPAC-POWR1014A-01TN48I ispPAC-POWR1014-01TN48I ispPAC-POWR1014A-02TN48I ispPAC-POWR1014-02TN48I ispPAC-POWR1014/A Data Sheet Operating Temperature Range I = Industrial (-40 Package T = 48-pin TQFP TN = Lead-Free 48-pin TQFP* Performance Grade 10V HVOUT 12V HVOUT Package ...

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... Lattice Semiconductor Package Options OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 ispPAC-POWR1014A 6 48-Pin TQFP 2-50 ispPAC-POWR1014/A Data Sheet 36 VMON9 35 VMON8 34 VMON7 VMON6 33 32 VMON5 31 GNDD 30 GNDA 29 VCCA 28 VMON4 27 VMON3 26 VMON2 25 VMON1 ...

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... Lattice Semiconductor Package Options (Cont.) OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 ispPAC-POWR1014/A Data Sheet ispPAC-POWR1014 6 48-Pin TQFP 2-51 36 VMON9 35 VMON8 34 VMON7 33 VMON6 32 VMON5 31 GNDD 30 GNDA 29 VCCA 28 VMON4 27 VMON3 26 VMON2 25 VMON1 ...

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... V pin usage clarification added. CCPROG VCCPROG pin usage further clarified. 2 Added Accessing I C Registers Through JTAG section. Added product information for the ispPAC-POWR1014-02 and ispPAC-POWR1014A-02. Added ESD Performance table. 2-52 ispPAC-POWR1014/A Data Sheet “SELTDI” changed to “TDISEL” frequency to 20 mA. ...