EL9112ILZ-T7 Intersil, EL9112ILZ-T7 Datasheet

IC DIFF RCVR/EQUALZR TRPL 28-QFN

EL9112ILZ-T7

Manufacturer Part Number
EL9112ILZ-T7
Description
IC DIFF RCVR/EQUALZR TRPL 28-QFN
Manufacturer
Intersil
Type
Receiverr
Datasheet

Specifications of EL9112ILZ-T7

Number Of Drivers/receivers
0/3
Protocol
Twisted-Pair
Voltage - Supply
5V
Mounting Type
Surface Mount
Package / Case
28-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Triple Differential Receiver/Equalizer
The EL9111 and EL9112 are triple channel differential
receivers and equalizers. They contains three high speed
differential receivers with five programmable poles. The
outputs of these pole blocks are then summed into an output
buffer. The equalization length is set with the voltage on a
single pin. Using the Enable pin on the EL9111 and EL9112,
the outputs can be placed into a high impedance state
enabling multiple devices to be connected in parallel and
used in a multiplexing application.
The gain can be adjusted up or down on each channel by 6dB
using its V
can be switched in to provide a matched drive into a cable.
The EL9111 and EL9112 have a bandwidth of 150MHz and
consume just 108mA on ±5V supply. A single input voltage is
used to set the compensation levels for the required length
of cable.
The EL9111 is a special version of the EL9112 that decodes
syncs encoded onto the common modes of three pairs of
CAT-5 cable by the EL4543. (Refer to the EL4543 datasheet
for details.)
The EL9111 and EL9112 are available in a 28 Ld QFN
package and are specified for operation over the full -40°C to
+85°C temperature range.
Pinouts
VSMO_G
VSMO_B
VSMO_R
VSPO_G
VOUT_G
VOUT_B
VSPO_B
VOUT_R
GAIN
1
2
3
4
5
6
7
8
control signal. In addition, a further 6dB of gain
(28 LD QFN)
TOP VIEW
THERMAL
EL9111
®
PAD
1
Data Sheet
22
21
20
19
18
17
16
15 VSM
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
VSP
VINM_B
VINP_B
VINM_G
VINP_G
VINM_R
VINP_R
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• 150MHz -3dB bandwidth
• CAT-5 compensation
• 108mA supply current
• Differential input range 3.2V
• Common mode input range -4V to +3.5V
• ±5V supply
• Output to within 1.5V of supplies
• Available in 28 Ld QFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Twisted-pair receiving/equalizer
• KVM (Keyboard/Video/Mouse)
• VGA over twisted-pair
• Security video
- 50MHz @ 1000 ft
- 125MHz @ 500 ft
VSMO_B
VSMO_G
VSMO_R
VSPO_G
VOUT_B
VSPO_B
VOUT_G
VOUT_R
All other trademarks mentioned are the property of their respective owners.
|
May 9, 2007
Intersil (and design) is a registered trademark of Intersil Americas Inc.
1
2
3
4
5
6
7
8
Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
(28 LD QFN)
TOP VIEW
THERMAL
EL9112
PAD
EL9111, EL9112
22
21
20
19
18
17
16
15 VSM
VSP
VINM_B
VINP_B
VINM_G
VINP_G
VINM_R
VINP_R
FN7450.4

Related parts for EL9112ILZ-T7

EL9112ILZ-T7 Summary of contents

Page 1

... VOUT_R EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. EL9111, EL9112 FN7450.4 EL9112 ...

Page 2

... EL9112IL-T13 9112IL EL9112ILZ (Note) 9112ILZ EL9112ILZ-T7 (Note) 9112ILZ EL9112ILZ-T13 (Note) 9112ILZ NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

Page 3

... Gain Gain 3 EL9111, EL9112 Thermal Information = +25°C) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C - -0. +0.5V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below S S http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +5V -5V +25°C, exposed die plate = -5V, unless otherwise specified ...

Page 4

Electrical Specifications PARAMETER DESCRIPTION ΔGain @ DC Channel-to-Channel Gain Matching ΔGain @ Channel-to-Channel Gain 15MHz Matching V(SYNC) High Level output on V/H HI (EL9111 only) V(SYNC) Low Level output on V/H LO (EL9111 only) SUPPLY ...

Page 5

Pin Descriptions (Continued) PIN EL9111IL NUMBER PIN NAME 21 VINM_B Blue negative differential input 22 VSP +5V to core of chip 23 HOUT Decoded Horizontal sync referenced to SYNCREF 24 VOUT Decoded Vertical sync referenced to SYNCREF 25 SYNCREF Reference ...

Page 6

Typical Performance Curves FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS V CABLE LENGTHS FIGURE 7. GROUP DELAY vs FREQUENCY FOR VARIOUS V CTRL FIGURE 9. OFFSET EL9111, EL9112 (Continued) AND CTRL CTRL FIGURE 6. CHANNEL MISMATCH FIGURE ...

Page 7

Typical Performance Curves -10 V =0.35V GAIN (ALL CHANNELS) V =0V -20 CTRL X =HIGH 2 -40 -60 -80 -100 100K 1M 10M FREQUENCY (Hz) FIGURE 11. COMMON-MODE REJECTION =0V CTRL V =0V GAIN -20 ...

Page 8

Typical Performance Curves FIGURE 17. GREEN CROSSTALK FIGURE 19. RED CROSSTALK FIGURE 21. RISE TIME AND FALL TIME 8 EL9111, EL9112 (Continued) FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE FIGURE 18. GREEN CROSSTALK FIGURE 20. RED CROSSTALK LENGTHS FN7450.4 May ...

Page 9

Typical Performance Curves FIGURE 23. TOTAL HARMONIC DISTORTION FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 9 EL9111, EL9112 (Continued) 1.2 0.8 0.6 0.4 0.2 FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD ...

Page 10

Applications Information Logic Control The EL9112 has two logical input pins, Chip Enable (ENABLE) and Switch Gain (X2). The logic circuits all have a nominal threshold of 1.1V above the potential of the logic reference pin (VREF). In most applications ...

Page 11

Decoding is based on the EL4543 encoding scheme, as described in Figure 27 and Table 1. The scheme is a three- level system, which has been designed such that the sum of the common mode voltages results in a fixed ...

Page 12

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 13

Package Outline Drawing L28.4x5A 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 10/06 4.00 PIN 1 INDEX AREA TOP VIEW PACKAGE BOUNDARY (2.65) (3.20) TYPICAL RECOMMENDED LAND PATTERN 13 EL9111, EL9112 A 0. 0.10 2X 0.50 ...

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