PEB24901HV1.2 Lantiq, PEB24901HV1.2 Datasheet

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Since April 1, 1999, Siemens Semiconductor is Infineon Technologies. The next revision of this document will be updated accordingly. ATTENTION ...

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ICs for Communications 4 Channel ISDN Echocancellation Digital Front End Quad IEC DFE-T PEB 24901 Version 1.1 Preliminary Data Sheet 2.95 T2490-111-P1-7600 ...

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PEB 24901 Revision History: Previous Releases: Page Subjects (changes since last revision) Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ...

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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Channel ISDN Echocancellation Digital Front End (Quad IEC DFE-T) Preliminary Data Sheet 1 Introduction The PEB 24901 4 Channel ISDN Echocancellation Digital Front End (Quad IEC DFE-T) is the digital part of an optimized ISDN 4B3T-U-Interface Line card chip ...

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Data speed conversion between the U received phase-wander µs peak to peak (CCITT Rec. Q.512). • Handling of commands and indications contained in the IOM-2 C/I-channel for activation, deactivation, supervision of power supply unit and ...

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Pinning and Outline D2A 33 D3A 34 D0B 35 N.C. 36 D1B 37 VDD 38 D2B 39 D3B 40 VSS 41 D0C 42 D1C 43 D2C 44 N.C. 45 D3C 46 D0D 47 D1D 48 Figure 1: Pin configuration ...

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Pin Definitions and Functions The following tables group the pins according to their functions. They include pin name, pin number, type, a brief description of the function, and cross-references referring to the sections in which the pin functions are ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Miscellaneous Function Pins 29 CLS0 O 20 CLS1 O 52 CLS2 O 61 CLS3 O 30 D0A O 35 D0B O 42 D0C O 47 D0D ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 43 D1C O 48 D1D O 33 D2A O 39 D2B O 44 D2C O 50 D2D O 34 D3A O 40 D3B O Semiconductor Group ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 46 D3C O 51 D3D RESQ I 55 SLOT I 28 ST00 I 27 ST01 I 26 ST10 I 24 ST11 ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 21 ST21 I 19 ST30 I 18 ST31 I 63 TP1 I 62 TP2 I 49 TP3 I 56 TSP I Interface to Analog Front End ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 10 PDM1 I 8 PDM2 I 7 PDM3 I 5 SDR I 17 SDX O Semiconductor Group Description Input of second-order sigma-delta ADC pulse density modulated ...

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System Integration The PEB 24901 Quad IEC DFE-T is optimized to work in conjunction with the PEB 24902 Quad IEC AFE on line modules in the central office or in the LT function of the access network . It ...

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IOM-2 DOUT DIN DCL FSC JTAG Boundary scan Figure 3: 8 channel LT application Semiconductor Group PDM 0..3 SDX PEB 24901 Quad IEC DFE-T SDR 15.36 MHz + 5V PEB 24901 SDX Quad IEC DFE-T SDR PDM 0..3 15 PEB ...

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Application Guide 3.1 Clock Generation In the exchange (LT mode) , all timing signals are derived from a system clock via the PLL internal to the PEB 24902 Quad IEC AFE. The master clock is generated with a crystal ...

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The IOM-2 interface is a four-wire serial interface with a data clock (DCL kHz frame synchronization clock (FSC), and one data line per direction: data downstream (DD) and data upstream (DU). The basic channel consists of a total ...

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As the PEB 24901 Quad IEC DFE-T occupies four IOM-slots, the DCL frequency should be at least 2048 KHz. The SLOT pin assigns either the IOM-slots the four channels (SLOT pin low), or ...

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P MADR = C 7 MAAR = 08 MACR = 48 SFI 1 = ISTA = 40 CIFIFO = 88 MAAR = 88 MACR = C8 MADR = 7 C Figure 6: C/I-Channel Use with the EPIC After the correct ...

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Monitor Channel The monitor channel represents a second method of initiating and reading Quad IEC DFE-T specific information. Features of the monitor channel are supplementary to the command/indicate channel. Unlike the command/indicate channel with an emphasis on status control, ...

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PEB 2055 and Monitor Channel Programming: P STAR = 25 MFFIFO = 1. Byte MFFIFO = 2. Byte STAR = 24 MFTC1 MFSAR = 04 CMDR = 08 STAR = 32 ISTA = 70 STAR = 26 MFFIFO ...

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The example of figure 7 demonstrates the use of EPIC-1 or EPIC-2 in the transmit-and- receive mode assumed that the transferred monitor message will be followed by a two byte confirmation issued by the Quad IEC DFE-T. Before ...

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This filter emulates the line characteristics in order to cancel the echoed data from the received signal and to regain the data from the far end. Because these coefficients characterize the line, being a time discrete pulse response, it ...

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Table 4 MONITOR Command to set the Driver pins (Hexadecimal Addresses) Hexadecimal Binary 81 7x 1000 0001 0111 3.2.1.2.4 Reading the Status Pins Each channel owns two status pins specifies the pin. Their ...

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The status on SDR is synchronised to SDX. Each time slot on SDR carries the corresponding LD bit during the last 12 bits of the slot. 13 bit 13 bit Slot 0 Slot ...

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SY: First bit of the time slots with transmission data. For synchronisation and bit allocation on SDX,SY is set to ONE on SDX and set to ZERO on SDR. LD: The Level-Detect bit indicates an analog signal being recognized at ...

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Boundary Scan All pins except the power supply pins, the "not connected" pins and pins TDI, TDO, TCK, TMS are included in the boundary scan. When the TAP controller is in the appropriate mode data is shifted into or out ...

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Boundary Scan Pin Number Number TDI ––> Semiconductor Group Pin ...

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Boundary Scan Pin Number Number TDI ––> Note: I/O pins are bidirectional only for device test purpose. For the function of these pins refer to section 1.2. TAP Controller The Test Access Port (TAP) controller implements the state ...

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EXTEST is used to examine the board interconnections. When the TAP controller is in the state "update DR", all output pins are updated with the falling edge of TCK. When it has entered state "capture DR" the levels of all ...

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Maintenance Functions 3.3.1 Loops For test of the line cards, several test loops are provided which can be controlled from the exchange. When a test loop is closed, all channels ( are looped back and ...

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BOUT and BIN. The input signal from the hybrid is ignored in this mode. These loops also are referred to as "analog loops". The analog loop mode is controlled via the IOM-2 C/I-channel analog loop, the transmit path ...

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LT (1 frame error detected in the NT and transmitted via M symbol). 3.4 Control Procedures A "Call-by-Call" activation or deactivation of the transmission link is provided for ISDN basic access deactivated ...

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The usage of the two input pins, RES and TSP has the same effect as inputs RES and SSP in the C/I-channel. They always overwrite the IOM-2 C/I-channel input. 3.4.1 Activation and Deactivation of Uk0 Transmission Lines On Uk0, the ...

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LT INFO U2W 2.133 ms NT INFO U1W 2.133 ms Figure 11 Procedure for Awake Downstream INFO U1W 2.133 ms NT INFO U2W 2.133 ms Figure 12 Procedure for Awake Upstream Semiconductor Group ...

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Procedures for Normal Activation with NT R IOM DID 3 DIU 3 RSYD 1.1 ARN 1.2 AIU 1.3 AIN 1.4 SBC IEC NT Downstream Figure 13 Activation of Uk0 Link Initiated by LT Semiconductor Group R U Line IOM ...

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R IOM DID 3 DIU 3 TIM 1.1 ARU 1.1 RSYD 1.1 ARN 1.2 AIU 1.3 (INFO U4H) AIN 1.4 SBC IEC NT Downstream Figure 14 Activation of Uk0 Link Initiated by NT Semiconductor Group R U Line IOM k0 ...

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Procedures for Normal Activation with NT-PBX or NT-TE R IOM DID 3 DIU 3 RSYD 1.1 ARN 1.2 AIN 1.4 ICC IEC NT-PBX, NT-TE Downstream Figure 15 Activation of Uk0 Link with NT-PBX or TE Initiated by LT Semiconductor ...

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R IOM DID 3 DIU 3 TIM 1.1 PU 1.1 ARU 1.1 RSYD 1.1 ARN 1.2 AIN 1.4 ICC IEC NT-PBX, NT-TE Downstream Figure 16 Activation of Uk0 Link with NT-PBX or TE Initiated by NT Semiconductor Group U Line ...

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Procedures for Activation of Loops R IOM U DID INFO 3 DIU INFO U0 3 SBC/ICC IEC NT Downstream Figure 17 Activation of Loop1 Semiconductor Group R Line IOM DID 3 3 DIU 3 3 IEC ...

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R IOM U DID INFO 3 DIU INFO 3 INFO INFO INFO U4 (INFO SBC IEC NT Downstream Figure 18 Activation of Loop 4 Semiconductor Group R Line IOM DID DIU 3 3 ...

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R IOM DID INFO 3 DIU INFO U0 3 INFO RSYD INFO U1W 1.1 INFO INFO U4 (INFO AR 2 INFO 1.2 AIU 1.3 INFO U3 (INFO U4H) AIL INFO U5 1.4 SBC IEC NT Downstream Figure 19 Activation of ...

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R IOM DID 3 DIU 3 RSYD 1.1 AR2 1.2 AI2 1.4 R IOM Data Looped Back ICC IEC NT-PBX, NT-TE Downstream Figure 20 Activation of Loop 2 within NT-PBX or TE Semiconductor Group U Line k0 INFO U0 3 ...

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R IOM DID 3 DIU 3 INFO INFO (INFO SBC IEC NT Downstream Figure 21 Activation of Loop 3 within NT-PBX or TE Semiconductor Group R U Line IOM k0 INFO U 0 DID 3 3 INFO U 0 DIU ...

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Procedure for Deactivation R IOM U Line INFO DR INFO U0 3.1 DIU 3.2 DID 3.2 SBC/ICC IEC NT Downstream Figure 22 Deactivation of Uk0 Link, always Initiated by LT 3.4.2 IOM-2 Control Information in the C/I-Channel The control ...

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Based on these protocols, control information is given downstream (directed from the exchange to the terminal equipment) or upstream (directed from the terminal equipment to the exchange) from one end point to the other via one or more parts of ...

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IOM-2 C/I codes for (DE-)Activation Upstream ARU 1000 Activation Request Upstream. The downstream unit of the IOM-2 interface has detected an awake signal on the line or requests activation layer 2 device. RDS 0111 Running ...

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IOM-2 C/I codes to the Quad IEC DFE-T for Test and Maintenance LTD 0011 Line Termination Disable. In the LT, the Quad IEC DFE-T stops transmitting signals (INFO U0) on the correwsponding channel, ignoring awake signals. The channel is ...

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Summary of IOM-2 Control Informations Table 8 Summary of Codes in C/I-Channel Code Command A1...A4 DIN LTD ...

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INFO U2 The LT (and LT-RP, if the NT-RP is synchronized) sends INFO U2 to enable the own echo canceller to adapt the coefficients, and with the Barker code the NT at the other end is enabled to synchronize. The ...

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INFO U4 INFO U4 means fully transparent data, the M-channel on Uk0 may be used to transfer loop commands and 1 kbit/s transparent data. INFO U5 INFO U5 means fully transparent data, the M-channel on Uk0 may be used to ...

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Deac. Acknowledge U0, DIU ARD DID Power Down DIU ARD { Start Awaking ARU (TE&/ARL) AWT } { 12 ms Awake Signal Sent U0, ARU (AWR&/ARL) (ARL&TE ...

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Transit Conditions and their Appreviations In the following list, C/I-channel infos are omitted. AWR Awake signal (INFO U1W or U2W) detected AWT INFO U1W of U2W has been sent out FRJ Frame jump, detected by receive or transmit buffer, ...

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The C/I-channel output and the transmitted Uk0 INFO are already specified by the state diagrams; below they are only referred to, if within a state there are more than one of them specified. In this case, the C/I-channel output and ...

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Frame jump In the transmit or in the receive data buffer a data over- or underflow has occurred. This is indicated to the associated layer 2 device with code FJ for 0 IOM-2 frames). The RDS counter and ...

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Synchronizing After successful awake procedure, the IEC tries to recognize INFO U1 (mode dependent). The user data ( pin DOUT is clamped to high. Start awaking Uk0 Receiving ARU or ARD in ...

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Technical Description 4.1 General The Uk0 interface is designed for data transmission on twisted pair wires in local telephone loops, with basic access to ISDN and a user bit rate of 144 kbit/s. Separation of the transmitted and received ...

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After successful synchronization, resynchronization will occur if the synchword is found to be consecutive 64 times in another position in the frame than the one expected after successful synchronization.The Quad IEC DFE-T is synchronized detects the synchword four ...

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Table 10 Frame Structure for Upstream Transmission 1/2 1/2 1 ...

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Table 11 MMS 43 Coding Table – – – – ...

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Table 12 4B3T Decoding Table + – – – 0 – – – – – + – – – + – ...

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The scrambler contains supervision circuitry to avoid the case of continuous output (1 or 0). This case can occur during activation if, for example, each stored bit in the scrambler is equal to the continuous data input. In this case, ...

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Figure 26 Descrambler in the LT without Local Loop Active Figure 27 ...

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Table 13 Coding of the Uk0-Signal Elements Upstream from INFO U1W: 16 times ternary + + + + + + + + – – – – – – – – A tone of: Frequency: 7.5 kHz Width: ...

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Awake Signal Detection To activate the Uk0 interface, special awake and acknowledge signals (INFO U1W and U2W) are defined. The activating Quad IEC DFE-T sends out a 7.5 kHz tone of 2.133 ms duration, which has to be detected ...

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Electrical Characteristics Unless otherwise specified, the static and dynamic limits apply over a supply voltage range from 4.75 to 5.25 V and over the temperature range as specified in section 6.2. 5.1 Static Requirements Table 14 Static Characteristics Parameter ...

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Dynamic Requirements preliminary values Figure 29: Dynamic Requirements (t.b.d) Table 15 Dynamic Input Characteristics Parameter Signal Clock rise / fall time CL15 Clock period CL15 Pulse width CL15 high / low Data rise / fall time Data setup Data ...

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Table 16 Dynamic Output Characteristics Parameter Signal t.b.d 5.3 Boundary Scan Timing preliminary values TCK TMS TDI TDO Parameter test clock period test clock period low test clock period high Semiconductor Group Symbol Limit Values min. typ. t TCP t ...

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Parameter TMS set-up time to TCK TMS hold time from TCK TDI set-up time to TCK TDI hold time from TCK TDO valid delay from TCK 5.4 Power Supply 5.4.1 Supply Voltages VDD to GND 5.4.2 Power Consumption All measurements ...

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It is not implied, that more than one of these conditions can be applied simultaneously. Table 18 Maximum ratings Parameter positive Supply Voltage Voltage applied at any input Voltage applied at any output Voltage between GNDx ...