T7115AMCD

Manufacturer Part NumberT7115AMCD
ManufacturerLSI
T7115AMCD datasheet
 

Specifications of T7115AMCD

Package TypePLCCLead Free Status / Rohs StatusNot Compliant
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April 1997
Features
Low-cost device for B-channel (64 kbits/s) or
D-channel (16 kbits/s) data transport.
Optional transparent mode—no HDLC framing is
performed.
Frame sync (FS) allows a slot-select feature to
access an individual time slot in any TDM data
stream (e.g., Lucent Technologies Microelectronics
Group Concentration Highway Interface [CHI] or
subset).
Bit-masking option allows effective data rates of 8,
16, 24, 32, 40, 48, and 56 kbits/s.
Maximum data rate up to 4.096 MHz.
Serial data-transfer pins for direct connection to the
Lucent ISDN line transceiver T7250C.
Supports IOM2, K2, GCI, and SLD interface.
Parallel microprocessor interface with either multi-
plexed or demultiplexed address and data lines for
easy interface with any microprocessor.
Single interrupt output signal with seven maskable
interrupt conditions.
Programmable interrupt modes.
Memory-mapped read and write registers.
TTL/CMOS compatible input/output.
3-state output pins to assist system diagnostics.
Low-power 1.25 m CMOS:
— 30 mW typical operation at 12 MHz.
— 5 mW standby mode (typical).
HDLC transceiver:
— Stand-alone HDLC framing operation.
— 64-byte FIFO in both transmit and receive direc-
tions.
— Supports block-move instruction.
— Multiple frames allowed in FIFO.
— Programmable FIFO full- and empty-level inter-
rupt.
T7121 HDLC Interface for ISDN (HIFI-64)
Description
The T7121 HDLC Interface for ISDN (HIFI-64) con-
nects serial communications links carrying HDLC bit-
synchronous data frames to 8-bit microcomputer sys-
tems. There is an optional transparent mode of oper-
ation in which no HDLC processing is performed on
user data. The device communicates with the system
microprocessor as a memory-mapped peripheral and
is controlled by reading and writing 19 internal regis-
ters. The chip can be instructed to interrupt the
microprocessor when it detects certain events requir-
ing microprocessor attention. The HDLC transmitter
and receiver are each buffered with 64-byte, first-in-
first-out (FIFO) memory storage. The 64-byte buffer
depth reduces the number of status polls or inter-
rupts to be processed by the microprocessor, improv-
ing overall system efficiency. The major blocks are
the microprocessor interface, transmit and receive
FIFO memory buffers, HDLC processor, and a con-
centration highway interface (see Figure 1). The
T7121 device is available in a 28-pin, plastic DIP or a
28-pin, plastic, small-outline, J-lead (SOJ) package
for surface mounting.

T7115AMCD Summary of contents

  • Page 1

    April 1997 Features Low-cost device for B-channel (64 kbits/s) or D-channel (16 kbits/s) data transport. Optional transparent mode—no HDLC framing is performed. Frame sync (FS) allows a slot-select feature to access an individual time slot in any TDM data stream ...

  • Page 2

    T7121 HDLC Interface for ISDN (HIFI-64) Contents Features ................................................................................................................................................................... 1 Description................................................................................................................................................................ 1 Pin Information ......................................................................................................................................................... 4 Functional Description .............................................................................................................................................. 8 Microprocessor Bus Interface ................................................................................................................................ 8 Addressing .......................................................................................................................................................... 8 Interrupts ............................................................................................................................................................. 8 Resets ................................................................................................................................................................. 9 FIFO Memory Buffers ............................................................................................................................................ 9 Transmit ...

  • Page 3

    Data Sheet April 1997 Description (continued) MICRO- PROCESSOR BUS INTERFACE RESET RD INTERNAL REGISTER WR BANK CS (R0—R15) (AR11—AR13) AND INT PARALLEL DATA I/O AD0—AD7 ALE A0—A3 Lucent Technologies Inc. T7121 HDLC Interface for ISDN (HIFI-64) MEMORY HDLC BUFFERS PROCESSING ...

  • Page 4

    T7121 HDLC Interface for ISDN (HIFI-64) Pin Information Table 1. Pin Assignments Group Chip Clock Power & Ground Microprocessor Bus Interface Serial Link Interface 4 ALE AD0 AD1 AD2 4 ...

  • Page 5

    Data Sheet April 1997 Pin Information (continued) Table 2. Pin Descriptions Pin Symbol Type 1 ALE I 2—5, AD0—AD7 I/O 7— — INT O 15 RESET ...

  • Page 6

    T7121 HDLC Interface for ISDN (HIFI-64) Pin Information (continued) Table 2. Pin Descriptions (continued) Pin Symbol Type 17 DXB/ O TSCA 18 CLKX I 19 DXA O 20 DRA I 6 Name/Function Transmit Data B or Time-Slot Control for DXA. ...

  • Page 7

    Data Sheet April 1997 Pin Information (continued) Table 2. Pin Descriptions (continued) Pin Symbol Type 21 CLKR/DRB I 23 CLK I 24, 25, 26, A3— — DD Lucent Technologies Inc. T7121 HDLC Interface for ISDN (HIFI-64) ...

  • Page 8

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description Microprocessor Bus Interface Addressing The T7121 is designed to easily interface with 8-bit microprocessors. The microprocessor bus interface allows parallel asynchronous access to a bank of 19 registers (R0—R15 and AR11—AR13). The ...

  • Page 9

    Data Sheet April 1997 Functional Description (continued) Resets The T7121 is fully reset by either asserting the RESET pin (hardware reset asserting both the TRES (R6—B5) and RRES (R6—B4) bits simultaneously when writing to register 6 (software reset). ...

  • Page 10

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Receive FIFO Data received from the serial link interface is stored in the 64-byte receive FIFO. In the HDLC mode, the receiver also places a status of frame (SF) status byte ...

  • Page 11

    Data Sheet April 1997 Functional Description (continued) When HWYEN = 1 and DXAC = 1, pin 17 is high. TSCA The transmitter begins transmission when the transmitter enable ENT bit (R6—B3) is set to 1. Once the ENT bit is ...

  • Page 12

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) CLKX DXA SET RESET CLOCK TRANSMITTER EDGES VIA R6—B5 VIA R9 The receiver can be enabled or disabled by programming the ENR bit (R6—B2). When disabled, the receiver ignores all serial ...

  • Page 13

    Data Sheet April 1997 Functional Description (continued) Time-Slot Feature The HIFI-64 can be configured to interface with devices supplying a frame-synchronization signal (FS) to indi- cate the beginning of a single or multiple time-slot sequence. The T7121 can be configured ...

  • Page 14

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Similarly for the receiver, the receive bit offset RBOF (R9—B[3—1]) and the receive time-slot offset RTSOF (R11—B[5—0]) determine where the first bit of the first receive time slot is found. The ...

  • Page 15

    Data Sheet April 1997 Functional Description (continued) TLBIT = 1 (TRANSMIT LSB FIRST) MSB LSB BIT 7 BIT TRANSMIT FIFO TRANSMITTER HDLC PROCESSES LSB FIRST MSB LSB BIT 7 BIT 0 ...

  • Page 16

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Bit Masking When in the TDM highway mode (HWYEN, R0—B7 = 1), the HIFI-64 can be programmed to mask any combina- tion of bits in a byte example, this ...

  • Page 17

    Data Sheet April 1997 Functional Description (continued) TLBIT = 1 (R13) TRANSMITTER BIT MASK (TRANSMIT LSB FIRST) MSB LSB BIT 7 BIT TRANSMIT FIFO TRANSMITTER HDLC PROCESSES LSB FIRST RLBIT = ...

  • Page 18

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) TLBIT = 0 (R13) TRANSMITTER BIT MASK (TRANSMIT MSB FIRST) TBM7 MSB LSB BIT 7 BIT TRANSMITTER HDLC TRANSMIT FIFO PROCESSES LSB ...

  • Page 19

    Data Sheet April 1997 Functional Description (continued) SLD and IOM2 Examples Example register settings for configuring to SLD, IOM2 TDM highways are shown below. These settings assume HWYEN (R0—B7 and FSPOL (R0—B6 Table 4. ...

  • Page 20

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Flags. All flags have the bit pattern 01111110 and are used for frame synchronization. The HIFI-64 automati- cally sends two flags between frames. If the FLAGS bit in the chip-configuration register ...

  • Page 21

    Data Sheet April 1997 Functional Description (continued) Transmitter FIFO Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor. However, all frames must be explicitly tagged with a Transmit Frame Complete (TFC) bit (R1—B7) ...

  • Page 22

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Bit 7 of the SF status byte is the CRC status bit incorrect CRC was detected, this bit is set the CRC was correct, the bit ...

  • Page 23

    Data Sheet April 1997 Functional Description (continued) Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are asynchronous events possible for a host read to put the number of ...

  • Page 24

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Transparent Mode The HIFI-64 can be programmed to operate in the transparent mode by setting the TRANS bit (AR11—B6 the transparent mode of operation, no HDLC processing is ...

  • Page 25

    Data Sheet April 1997 Functional Description (continued) Programming Note: The match bit (MATCH) affects both the transmitter and the receiver. Care should be taken to correctly program both the transmit idle character and the receive match character before setting MATCH. ...

  • Page 26

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) In the local loopback mode: CLKRI (R9—B0) must equal CLKXI (R9—B4). We recommend changing CLKRI to match CLKXI (other highway parameters need not be altered). CLKX clocks both the transmitter and ...

  • Page 27

    Data Sheet April 1997 Functional Description (continued) In the remote loopback mode: CLKR must equal or be synchronous with CLKX. We recommend clocking both transmit and receive data with CLKX (R5—B6 set to 1). Receive and transmit bit masks (R12 ...

  • Page 28

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) 3-State Mode The HIFI-64 can be placed in a high-impedance mode for test purposes. In this configuration, all output pins are placed in a 3-state condition. This can be accomplished in ...

  • Page 29

    Data Sheet April 1997 Functional Description (continued) Table 6. HIFI-64 Register Summary Reg# R/W Bit 7 R0 R/W HWYEN R1 R/W TFC R2 R TED R3 R/W DATA7 R4 R EOF R5 R/W P17CTL R6 R/W PDWN R7 R/W DXAC ...

  • Page 30

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 7. Register R0—Chip Configuration Register R0—B7 R0—B6 R0—B5 HWYEN FSPOL (0)* (1) Register Bit Symbol R0 B0 DINT R0 B1 IPOL R0 B2 FLAGS ALT ...

  • Page 31

    Data Sheet April 1997 Functional Description (continued) Table 8. Register R1—Transmitter Control Register R1—B7 R1—B6 R1—B5 TFC TABT (0) (0) Register Bit Symbol R1 B(0—5) TIL0—TIL5 Transmitter Interrupt Level. These bits specify the minimum number of R1 B6* TABT R1 ...

  • Page 32

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 9. Register R2—Transmitter Status Register R2—B7 R2—B6 R2—B5 TED TQS6 TQS5 (1) (1) Register Bit R2 B(0— Table 10. Register R3—Data Byte Register R3—B7 R3—B6 R3—B5 DATA7 DATA6 ...

  • Page 33

    Data Sheet April 1997 Functional Description (continued) Table 11. Register R4—Receiver Status Register R4—B7 R4—B6 R4—B5 EOF RQS6 RQS5 (0) (0) Register Bit Symbol R4 B(0—6) RQS0—RQS6 Receive Queue Status. Read only. Bits 0—6 indicate how many bytes R4 B7 ...

  • Page 34

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 12. Register R5—Receiver Control Register R5—B7 R5—B6 R5—B5 P17CTL P21CTL RIL5 (0) (0) Register Bit Symbol R5 B(0—5) RIL0—RIL5 R5 B6 P21CTL R5 B7 P17CTL 34 R5—B4 R5—B3 RIL4 RIL3 ...

  • Page 35

    Data Sheet April 1997 Functional Description (continued) Table 13. Register R6—Operation Control Register R6—B7 R6—B6 R6—B5 PDWN 3STATE TRES (0) (0) Register Bit Symbol R6 B0* RLOOP R6 B1* LLOOP R6 B2 ENR R6 B3 ENT R6 B4 RRES † ...

  • Page 36

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 14. Register R7—Transmit Time-Slot Control Register R7—B7 R7—B6 R7—B5 DXAC DXBC TSLT5 (0) (0) Register Bit Symbol R7 B(0—5) TSLT0—TSLT5 R7 B6* R7 B7* * The HIFI-64 can transmit on ...

  • Page 37

    Data Sheet April 1997 Functional Description (continued) Table 16. Register R9—Bit Offset Control Register R9—B7 R9—B6 R9—B5 TBOF2 TBOF1 TBOF0 (0) (0) Register Bit Symbol R9 B0 CLKRI R9 B(1—3) RBOF0—RBOF2 Receiver Bit Offset. These 3 bits provide a fixed ...

  • Page 38

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 17. Register R10—Transmitter Time-Slot Offset Control Register R10—B7 R10—B6 R10—B5 DXI TLBIT TTSOF5 (0) (1) Register Bit R10 B(0—5) TTSOF0—TTSOF5 Transmitter Time-Slot Offset. The value of these 6 bits, R10 ...

  • Page 39

    Data Sheet April 1997 Functional Description (continued) Table 18. Register R11—Receiver Time-Slot Offset Control Register R11—B7 R11—B6 R11—B5 DRI RLBIT RTSOF5 (0) (1) Register Bit Symbol R11 B(0—5) RTSOF0—RTSOF5 Receiver Time-Slot Offset. The value of these 6 bits, coded in ...

  • Page 40

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 19. Alternate Register AR11—Transparent-Mode Control Register AR11—B7 AR11—B6 AR11—B5 TEST TRANS MATCH (0) (0) Register Bit Symbol AR11 B(0—2) OCTOF0—OCTOF2 Octet Bit Offset. Read only. These bits record the offset ...

  • Page 41

    Data Sheet April 1997 Functional Description (continued) Table 20. Register R12—Receiver Mask Register R12—B7 R12—B6 R12—B5 RBM7 RBM6 RBM5 (1) (1) Register Bit Symbol R12 B(0—7) RBM0—RBM7 Receiver Time-Slot Bit Mask. This register allows the HIFI-64 to pro- Table 21. ...

  • Page 42

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 22. Register R13—Transmitter Mask Register R13—B7 R13—B6 R13—B5 TBM7 TBM6 TBM5 (0) (0) Register Bit Symbol R13 B(0—7) TBM0—TBM7 Transmitter Time-Slot Bit Mask. This register allows the HIFI-64 to Table ...

  • Page 43

    Data Sheet April 1997 Functional Description (continued) Table 24. Register R14—Interrupt Mask Register R14—B7 R14—B6 R14—B5 TBCRC RIIE ROVIE (0) (0) Register Bit Symbol R14 B0 TDIE R14 B1 TEIE R14 B2 UNDIE R14 B3 RFIE R14 B4 REOFIE Receive ...

  • Page 44

    T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Table 25. Register R15—Interrupt Status Register R15—B7 R15—B6 R15—B5 0 RIDL OVERUN (–) (0) Register Bit Symbol R15 B0 TDONE R15 B1 TE R15 B2 UNDABT R15 B3 RF R15 B4 ...

  • Page 45

    Data Sheet April 1997 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...

  • Page 46

    T7121 HDLC Interface for ISDN (HIFI-64) Clock Characteristics System Clock Input (CLK): 0 MHz—12 MHz. Transmit Data Clock (CLKX): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz. Receive Data Clock (CLKR): no minimum frequency*, <CLK/2 maximum frequency to 4.096 ...

  • Page 47

    Data Sheet April 1997 Timing Characteristics (continued) FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR CLKX/CLKR FS ( DXA/B (CLKXI = 0) TSCA DRA/B (CLKRI = 0) Figure 13. Bit Masking, Bit 2 Masked for Transmit, Bit 6 ...

  • Page 48

    T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR CLKX/CLKR FS ( FIRST BIT TRANSMITTED DXA/B 0 (CLKXI = 1) TSCA DRA/B (CLKRI = 0) FRAME SYNC SAMPLED ON THIS ...

  • Page 49

    Data Sheet April 1997 Timing Characteristics (continued) FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR CLKX/CLKR FS ( FIRST BIT TRANSMITTED DXA/B (CLKXI = 0) TSCA DRA/B (CLKRI = 0) FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR ...

  • Page 50

    T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR CLKX/CLKR FS ( FIRST BIT TRANSMITTED DXA/B (CLKXI = 0) TSCA DRA/B (CLKRI = 1) FRAME SYNC SAMPLED ON THIS EDGE ...

  • Page 51

    Data Sheet April 1997 Timing Characteristics (continued) Multiplexed Address and Data Both address and data on AD7—AD0. Table 26. Multiplexed Address and Data Symbol on Name Diagram A tALHALL ALE Pulse Width B tADVALL Address Valid to ALE Low C ...

  • Page 52

    T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) ALE CS AD7—AD0 WR RD AD7—AD0 CLK Figure 21. Timing for Multiplexed Address/Data ADDRESS Data Sheet April 1997 DATA ...

  • Page 53

    Data Sheet April 1997 Timing Characteristics (continued) Separate Address and Data Address on A3—A0, data on AD7—AD0. Table 27. Separate Address and Data Symbol on Name Diagram A tALHCSL ALE High to B tRWHALL RD C tAVRDL Address Valid to ...

  • Page 54

    T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) ALE CS AD3—AD0 AD7—AD0 WR RD AD7—AD0 CLK Figure 22. Timing for Separate Address/Data Data Sheet April 1997 ...

  • Page 55

    Data Sheet April 1997 Timing Characteristics (continued) Concentration Highway Table 28. Concentration Highway Timing for CMS = 0 Symbol on Name Diagram A tDCLDCL CLKX/R Period B tFSHCKE FS High to CLKX/R Edge Selected C tCKEFSL FS Hold After CLKX/R ...

  • Page 56

    T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) CLKX CLKR FS ( DXA AND/OR DXB 3 (CLKXI = 0) TSCA DRA OR DRB 3 (CLKRI = 1) (CMS = 0, CLKXI = 0, CLKRI = 1, FSPOL ...

  • Page 57

    Data Sheet April 1997 Timing Characteristics (continued) CLKX CLKR FS ( DXA AND/OR DXB 3 (CLKXI = 1) TSCA DRA OR DRB 3 (CLKRI = 0) (CMS = 0, CLKXI = 1, CLKRI = 0, FSPOL = 1, ...

  • Page 58

    T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) Table 29. Concentration Highway Timing for CMS = 1 Symbol on Name Diagram A tDCLDCL CLKX/R Period B tFSHCKE FS High to CLKX/R Edge Selected C tCKEFSL FS Hold After CLKX/R ...

  • Page 59

    Data Sheet April 1997 Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a ...

  • Page 60

    T7121 HDLC Interface for ISDN (HIFI-64) Outline Diagrams 28-Pin, Plastic DIP Dimensions are in millimeters. Controlling dimensions are in inches PIN #1 IDENTIFIER ZONE 2.54 TYP Number of Package Pins Description PDIP6 (Plastic Dual In-Line Package) "0.600" ...

  • Page 61

    Data Sheet April 1997 Outline Diagrams (continued) 28-Pin, Plastic SOJ, Surface Mounting Dimensions are in millimeters. Controlling dimensions are in inches PIN #1 IDENTIFIER ZONE 1.27 TYP Number of Package Pins Description SOJ (Small-Outline J-Lead) Lucent Technologies ...

  • Page 62

    T7121 HDLC Interface for ISDN (HIFI-64) Ordering Information Device Code T7121-PL2 T7121-EL2 62 Package 28-Pin, Plastic DIP 28-Pin, Plastic SOJ Data Sheet April 1997 Temperature – +85 C – +85 C Lucent Technologies Inc. ...

  • Page 63

    Data Sheet April 1997 Appendix This Appendix is intended to answer questions that may arise when using the T7121 HDLC Interface for ISDN. These questions have been compiled from cus- tomer inquiries. The questions and answers are divided into four ...

  • Page 64

    T7121 HDLC Interface for ISDN (HIFI-64) Appendix (continued) Q8: The T7121 is in HDLC mode, and the software views the transmit FIFO byte x 2 FIFO. When the TE and TDONE are enabled: 1. After initializing, when ...

  • Page 65

    Data Sheet April 1997 Appendix (continued) Q14: Does TLBIT (R10, b6) reorder the CRC bits? A14: Yes, the TLBIT operates on every byte, including the CRC. Q15: When transmitting multiple frames neces- sary to wait until one frame ...

  • Page 66

    T7121 HDLC Interface for ISDN (HIFI-64) Appendix (continued) Power and Ground Q20: Are there any warning signs that indicate poor grounding practices have been used? A20: If errors occur which do not appear to be due to software or to ...

  • Page 67

    Data Sheet April 1997 Notes Lucent Technologies Inc. T7121 HDLC Interface for ISDN (HIFI-64) 67 ...

  • Page 68

    T7121 HDLC Interface for ISDN (HIFI-64) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, ...