T7115AMCD LSI, T7115AMCD Datasheet - Page 12

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T7115AMCD

Manufacturer Part Number
T7115AMCD
Description
Manufacturer
LSI
Datasheet

Specifications of T7115AMCD

Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
The receiver can be enabled or disabled by programming the ENR bit (R6—B2). When disabled, the receiver
ignores all serial inputs (i.e., no data loaded into the FIFO). Whatever was in the FIFO before the receiver was dis-
abled remains intact, and the microprocessor can read the contents as normal. Disabling the receiver does not
cause a receiver reset. Whenever the receiver has been enabled and is subsequently disabled, the receiver must
be reset via RRES (R6—B4) before it is reenabled.
The HIFI-64 can receive data on either of two receive data pins (DRA, pin 20, or DRB, pin 21) depending on the
programming of the DRA/B bit in register 8 (R8—B7). The HIFI-64 can be programmed to use either the input of pin
21 (CLKR/DRB) or the input of pin 18 (CLKX) as the receive clock using P21CTL (R5—B6). Clearing P21CTL to 0
(DEFAULT) selects pin 21, while a setting of 1 selects pin 18. The selected clock can be programmed to latch
received data on either clock edge using CLKRI (R9—B0). Setting CLKRI to 1 causes the receiver to use the posi-
tive receive clock edge to latch data, while clearing CLKRI to 0 causes the receiver to use the negative edge.
Whenever the clock edge is changed, the receiver should be reset via an RRES (R6—B4). When a gated clock is
used, the receiver begins latching data on the first programmed clock edge. When a gated clock is used, separate
transmit and receive clocks must be used if data alignment to the first clock edge is required, since the transmit
clock requires an extra edge to align. See Figures 3 and 4.
12
CLKR
DRA
EDGES
CLOCK
VIA R9
CLKX
SET
DXA
CLOCK
EDGES
VIA R9
SET
VIA R6—B4
RECEIVER
RESET
TRANSMITTER
VIA R6—B5
B0
RESET
(continued)
LATCH IN 1ST RECEIVE BIT ON 1ST NETGATIVE EDGE AFTER RECEIVE RESET
Figure 3. Transmitting with a Gated Clock
Figure 4. Receiving with a Burst Clock
TRANSMIT 1ST BIT ON 1ST POSITIVE EDGE AFTER 1ST NEGATIVE EDGE
FIRST DATA BYTE
FIRST BYTE TRANSMITTED
UNTIL NEXT EDGE
B7
MAINTAINED
BIT VALUE
B0
SECOND BYTE TRANSMITTED
SECOND DATA BYTE
Lucent Technologies Inc.
B7
Data Sheet
April 1997
5-5029
5-5030

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