T7115AMCD LSI, T7115AMCD Datasheet - Page 14

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Similarly for the receiver, the receive bit offset RBOF (R9—B[3—1]) and the receive time-slot offset RTSOF
(R11—B[5—0]) determine where the first bit of the first receive time slot is found. The time slot used is selected by
the value of the receiver time-slot RSLT (R8—B[5—0]). The first bit is received
RBOF + (8 x RTSOF) + (8 x RSLT) = M
bit times after the beginning of the TDM frame. Figure 5 illustrates using the offsets to configure a system consist-
ing of four time slots, where the initial time slot aligns with the FS. For this system, FE = 0, CLKXI = 1, CLKRI = 0,
TSLT = 000000, and RSLT = 000001.
Transmission During Unassigned Time Slots
During time slots when the HIFI-64 is not transmitting, the transmit data output 3-states (an external pull-up resistor
is recommended). This also occurs during masked bit times during a time slot (see the Bit Masking section). If pin
17 is configured to
times in the assigned time slot.
Bit Order During Transmission
Data transmission is normally least significant bit (LSB) first per HDLC protocol specifications. In transparent mode,
data is also generated least significant bit first. However, when in the TDM highway mode (HWYEN R0—B7 = 1),
the order of transmission and the expected order for receiving can be reversed by programming the TLBIT and
RLBIT (R10—B6) and (R11—B6), respectively. These bits can be programmed independently of one another. In
other words, the HIFI-64 can be receiving LSB first but transmitting most significant bit (MSB) first, or vice versa.
The effect of TLBIT cleared to 0 is to reverse end-for-end the transmitter-generated data before transmission in the
time slot. All data is reversed, including flags, aborts, CRC, and user data. The effect of RLBIT cleared to 0 is to
reverse end-for-end the time-slot data before passing it to the receiver. RLBIT and TLBIT have no effect on the data
unless HWYEN (R0—B7) = 1.
Figures 6 and 7 show how the transmission and reception of data is affected by adjusting TLBIT and RLBIT. The
convention used represents user data in the FIFO with lower-case letters and HDLC data as upper-case letters.
This convention is meant to indicate only that data in the FIFO and data transmitted or received during the time
slot(s) may not be identical bit-for-bit (i.e., zero-bit insertion and deletion—see the HDLC section of this document).
14
TDM DATA
CLKX
CLKR
FS
Figure 5. Maximum Bit and Time-Slot Offsets for a Four Time-Slot System
TSCA
FS LATCHED ON THIS EDGE
,
TBOF = 111
RBOF = 111
TSCA
TS 0
is high during all time slots other than the assigned time slot and during masked bit
(continued)
TS 1
RTSOF = 000011
TTSOF = 000011
TS 2
TS 3
FIRST BIT TRANSMITTED
TS 0
Lucent Technologies Inc.
Data Sheet
RECEIVED
FIRST BIT
April 1997
TS 1
5-5031