T7115AMCD LSI, T7115AMCD Datasheet - Page 19

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Functional Description
SLD and IOM2 Examples
Example register settings for configuring to SLD, IOM2, or K2 TDM highways are shown below. These settings
assume HWYEN (R0—B7) = 1 and FSPOL (R0—B6) = 1.
Table 4. Example Register Settings
HDLC Operation
This section describes the standard HDLC functions performed by the HIFI-64. HDLC operation is the default
mode of operation. The transmitter accepts parallel data from the transmit FIFO, converts it to a serial bit stream,
provides bit stuffing as necessary, adds the CRC and the opening and closing flags, and sends the framed serial
bit stream on the selected transmit data pin(s). The receiver accepts serial data on the selected receive data pin,
identifies frames for proper format, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel
data in the receive FIFO. HDLC frames on the serial link have the following format:
All bits between the opening flag and the CRC are considered user data bits. User data bits such as the address,
control, and information fields for LAPB or LAPD frames are fetched from the transmit FIFO for transmission.
Received user data bits are stored in the FIFO buffers. The 16 bits preceding the closing flag are the frame check
sequence or cyclic redundancy check (CRC) bits.
Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing)
The HDLC protocol recognizes three special bit patterns: flags, aborts, and idles. These patterns have the com-
mon characteristic of containing at least six consecutive 1s. A user data byte can contain one of these special pat-
terns. Transmitter zero-bit stuffing is done on user data and CRC fields of the frame to avoid transmitting one of
these special patterns. Whenever five 1s occur between flags, a 0 bit is automatically inserted after the fifth 1, prior
to transmission of the next bit. On the receive side, if five successive 1s are detected followed by a 0, the 0 is
assumed to have been inserted and is deleted (bit destuffing).
FE, (R0—B5)
P21CTL, (R5—B6)
CMS, (R8—B6)
CLKXI, (R9—B4)
TBOF[2—0], (R9—B[7—5])
TTSOF[5 0], (R10—B[5—0])
TSLT[5—0], (R7—B[5—0])
CLKRI, (R9—B0)
RBOF[2—0], (R9—B[3—1])
RTSOF[5—0], (R11—B[5—0])
RSLT[5—0], (R8—B[5—0])
Opening Flag
01111110
Register
User Data Field
(continued)
(# of time slots) – 1
(# of time slots) – 1
8 bits
Desired time slot
Desired time slot
IOM2/GCI
111
111
0
1
1
1
0
Frame Check Sequence (CRC)
000000—000011
000100—000111
T7121 HDLC Interface for ISDN (HIFI-64)
16 bits
000011
000011
SLD
111
111
0
1
0
1
0
000001—000111, 000000
000001—000111, 000000
000000, 000111
000000, 000111
Closing Flag
01111110
111
111
K2
0
1
0
1
0
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