T7115AMCD LSI, T7115AMCD Datasheet - Page 20

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Flags. All flags have the bit pattern 01111110 and are
used for frame synchronization. The HIFI-64 automati-
cally sends two flags between frames. If the FLAGS bit
in the chip-configuration register (R0—B2) is cleared to
0, the 1s idle byte (11111111) is sent between frames if
no data is present in the FIFO. Once there is data in the
transmit FIFO, an opening flag is sent followed by the
frame. If the FLAGS bit (R0—B2) is set to 1, the HIFI-
64 sends continuous flags when the transmit FIFO is
empty. During transmission, two successive flags will
not share the intermediate 0. The HIFI-64 does not
transmit consecutive frames with a shared flag.
An opening flag is generated at the beginning of a
frame (indicated by the presence of data in the transmit
FIFO and the transmitter enabled). Data is transmitted
per the HDLC protocol until a byte is read from the
FIFO with TFC set. The HIFI-64 follows this byte with
the CRC sequence and a closing flag.
The receiver recognizes the 01111110 pattern as a
flag. Two successive flags may or may not share the
intermediate 0 bit and are identified as two flags (i.e.,
both 011111101111110 and 0111111001111110 are
recognized by the HIFI-64). The received data bytes
are stored in the 64-byte receive FIFO delayed by three
bytes or delayed by four bytes if operating in the TDM
highway mode (i.e., HWYEN, R0—B7 = 1). When
another flag is identified, it is treated as the closing flag.
As mentioned above, a flag sequence in the user data
or FCS fields is prevented by zero-bit insertion and
deletion. The received CRC bytes are not loaded into
the receive FIFO. The HIFI-64 receiver recognizes a
single flag between frames as both a closing and open-
ing flag.
Aborts. The bit pattern of the abort sequence is
01111111, with 0 transmitted first. A frame can be
aborted by writing a 1 to TABT (R1—B6). This causes
the last byte written to the transmit FIFO to be replaced
with the abort sequence upon transmission. Once a
byte is tagged by a write to TABT, it cannot be cleared
by subsequent writes to R1. TABT (R1—B6) and TFC
(R1—B7) should never be set to 1 simultaneously
since this causes the transmitter to enter an invalid
state that requires a transmitter reset to clear. A frame
should not be aborted in the very first byte following the
opening flag. An easy way to avoid this situation is to
first write a dummy or junk byte into the queue and then
write the abort command to the queue.
When receiving a frame, the receiver recognizes the
abort sequence whenever it receives a 0 followed by
seven consecutive 1s. This status results in the abort
bit, and possibly the bad byte count bit and/or bad CRC
20
20
(continued)
bits, being set in the Status of Frame status byte which
is appended to the receive data queue. The last two
bytes of user data are assumed to be CRC bits and are
not placed in the queue. All subsequent bytes are
ignored until a valid opening flag is received.
Idles. In accordance with the HDLC protocol, the HIFI-
64 recognizes 15 or more contiguous received 1s as
idle. When the HIFI-64 receives 15 contiguous 1s, the
receiver idle bit (RIDL, R15—B6) is set in register 15.
An interrupt pin transition is generated if no other
unmasked interrupts are active and the RIDL interrupt
is unmasked; i.e., RIIE (R14—B6) = 1.
For transmission, the 1s idle byte is defined as the
binary pattern 11111111 (FF hexadecimal). If the
FLAGS control bit in the chip configuration register
(R0—B2) is 0, the 1s idle byte is sent as the time-fill
byte between frames. A time-fill byte is sent when the
transmit FIFO is empty and the transmitter has com-
pleted transmission of all previous frames. Frames are
sent back-to-back otherwise. If the FLAGS bit (R0—B2)
is set to 1, flags (01111110) are sent as the time-fill
byte between frames. 1s idle is the default time-fill byte.
Note: Regardless of the time-fill byte used, there
CRC. For a given frame of bits, 16 additional bits that
constitute an error-detecting code are added by the
transmitter. As called for in the HDLC protocol, the
Frame Check Sequence bits are transmitted most sig-
nificant bit first and are bit stuffed. The Cyclic Redun-
dancy Check (or Frame Check Sequence) is calculated
as a function of the transmitted bits by using the ITU-T
standard polynomial:
x
At the other end, the receiver performs the same calcu-
lation on the received bits after destuffing and com-
pares the results to an expected result. An error occurs
if, and only if, there is a mismatch.
The transmitter can be instructed to transmit a cor-
rupted CRC by setting the Transmit Bad CRC bit
TBCRC (R14—B7). As long as the TBCRC bit is set,
the CRC is corrupted for each frame transmitted by log-
ically flipping the least significant bit of the transmitted
CRC.
The receiver calculates and verifies the CRC for an
incoming frame. The result of the CRC check is
reported in bit 7 of the Status of Frame byte which is
placed in the receive FIFO after the last data byte of
the frame. The CRC is not stored in the FIFO.
16
+ x
always is an opening and closing flag with each
frame. Back-to-back frames are separated by
two flags.
12
+ x
5
+ 1
Lucent Technologies Inc.
Data Sheet
April 1997