T7115AMCD LSI, T7115AMCD Datasheet - Page 24

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Transparent Mode
The HIFI-64 can be programmed to operate in the
transparent mode by setting the TRANS bit
(AR11—B6) to 1. In the transparent mode of operation,
no HDLC processing is performed on user data. The
transparent mode can be exited at any time by clearing
the TRANS bit to 0. It is recommended that the trans-
mitter be disabled (ENT, R6—B3 = 0) when changing in
and out of transparent mode. The transmitter should be
reset by a TRES whenever the mode is changed.
Three alternate registers are provided to control opera-
tion in the transparent mode:
AR11—Transparent Mode Control
AR12—Receive Match Character
AR13—Transmitter Idle Character
The alternate registers are accessed by setting the ALT
bit (R0—B4) to 1. All subsequent addressing of regis-
ters 11 through 13 then refer to the alternate registers
(AR11—AR13). Returning to the foreground register
set is accomplished by clearing the ALT bit (R0—B4) to
0.
In the transmit direction, the HIFI-64 takes data from
the transmit FIFO and transmits that data exactly bit for
bit on the DXA pin, the DXB pin, or both, depending on
the configuration of the DXAC and DXBC bits in regis-
ter 7 (R7—B6, B7). When there is no data in the trans-
mit FIFO, the HIFI-64 either transmits all 1s, or
transmits the transmitter idle character programmed in
AR13 if the MATCH bit (AR11—B5) is set to 1. To
cause the transmit idle character to be sent first, the
character must be programmed in AR13 before the
transmitter is enabled. In non-TDM highway modes,
the transmit idle character or the 1s idle character
is always sent first, even if data is present in the
FIFO. In TDM highway mode, the first character trans-
mitted is FF hexadecimal regardless of the mode. The
bits are transmitted least significant bit first in non-TDM
highway mode (HWYEN, R0—B7 = 0). In TDM highway
modes (HWYEN = 1), the TLBIT (R10—B6) deter-
mines the bit transmission order. Subrate operation
using the transmit bit mask is also supported. The
transmitter empty (TE) interrupt acts normal.
The transmitter-done interrupt (TDONE) is used to
report an empty transmit FIFO. The TDONE interrupt
thus provides a way to determine transmission end. In
transparent mode, a TDONE interrupt is generated
when the transmitter is reset, as does a TE interrupt.
The UNDABT interrupt is not active in transparent
mode.
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(continued)
If the HIFI-64 is in the TDM highway mode (HWYEN,
R0—B7 = 1), transmit data is octet-aligned to the
selected time slot. If HWYEN = 0, transmit data is
octet-aligned to the first CLKX after the transmitter has
been enabled (ENT, R6 B3 = 1). See Figure 3 for
details of clock start-up in non-TDM highway modes.
In the receive direction, the HIFI-64 loads received data
from the DRA or DRB pin (depending on the configura-
tion of the DRA/B bit in register 8 [R8—B7]) directly into
the receive FIFO bit for bit. In non-TDM highway
modes, the data is assumed to be least significant bit
first. In TDM highway mode, the RLBIT (R11 B6) con-
trols the bit order. If the MATCH bit (AR11—B5) is 0,
the receiver begins loading data into the receive FIFO,
beginning with the first CLKR detected after the
receiver has been enabled (ENR, R6—B2 = 1). If the
MATCH bit (AR11—B5) is set to 1, the receiver does
not begin loading data into the FIFO until the receiver
match character programmed in AR12 has been
detected. The search for the receiver match character
is in a sliding window fashion if the ALOCT (Align to
Octet) bit (AR11—B4) is 0, or only on octet boundaries
if the ALOCT bit is set to 1. The octet boundary is
aligned to the receive time slot if HWYEN (R0—B7) = 1
or relative to the first CLKR after the receiver has been
enabled (ENR, R6—B2 = 1), if HWYEN (R0—B7) = 0.
The matched character and all subsequent bytes are
placed in the receive FIFO. A receiver reset RRES
causes the receiver to realign to the match character if
MATCH is set.
The receiver full (RF) and receiver overrun (OVERUN)
interrupts act as normal. The received end of frame
(REOF) and receiver idle (RIDL) interrupts are not
used in the transparent mode. The match status
(MSTAT) bit (AR11—B4) is set to 1 when the receiver
match character is first recognized. If the MATCH bit
(AR11—B5) is 0, the MSTAT bit (AR11—B4) is set to 1
automatically when the first bit is received, and the
octet offset status bits (AR11—B[0—2]) read 000. If the
MATCH bit (AR11—B5) is programmed to 1, the
MSTAT bit (AR11—B4) is set to 1 upon recognition of
the first receiver match character, and the octet offset
status bits (AR11—B[0—2]) indicate the offset relative
to the octet boundary at which the receiver match char-
acter was recognized. The octet offset status bits have
no meaning until the MSTAT bit is set to 1. An octet off-
set of 111 indicates byte alignment.
An interrupt for recognition of the match character can
be generated by setting the RIL level to 1. Since the
matched character is the first byte written to the FIFO,
the RF interrupt occurs with the writing of the match
character to the receive FIFO.
Lucent Technologies Inc.
Data Sheet
April 1997