T7115AMCD LSI, T7115AMCD Datasheet - Page 32

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Table 9. Register R2—Transmitter Status Register
Table 10. Register R3—Data Byte Register
Note: A special block-move mode allows data to be loaded as a block to the FIFO. A block move is accomplished only in the MUXed address
32
Register
Register
R2—B7
R3—B7
DATA7
R2
R2
TED
R3
and data mode by setting the BM bit in register 0 (R0—B3) to 1 and holding AD6 high during the address cycle of the ALE. All writes then
go directly to the transmit FIFO and all reads address the receive FIFO. Normal ALE mode addressing is accomplished by holding AD6
low during the ALE address cycle. Block move is enabled and disabled by the BM bit in register 0 (R0—B3).
(1)
B(0—7)
B(0—6)
R2—B6
R3—B6
Bit
DATA6
TQS6
Bit
B7
(1)
DATA0—DATA7
Symbol
R2—B5
R3—B5
DATA5
(continued)
TQS5
TQS0—TQS6
(1)
Symbol
TED
The user data bytes to be transmitted are loaded through this register
(write). Also, the user data bytes received are accessed through this
register (read).
R2—B4
R3—B4
DATA4
TQS4
(1)
Transmit Queue Status. Read only. Bits 0—6 indicate how
many bytes can be added to the transmit FIFO. The bits are
encoded in binary, with bit 0 being the LSB.
Transmitter Empty Dynamic. Read only. When this bit is
high, it indicates that the number of empty locations available
in the transmit FIFO is greater than or equal to the value pro-
grammed in the TIL bits (see register 1). This bit is cleared only
when the transmit FIFO is loaded above the preprogrammed
empty-trigger level.
R2—B3
R3—B3
DATA3
TQS3
(1)
Name/Function
Name/Function
R2—B2
R3—B2
DATA2
TQS2
(1)
R2—B1
R3—B1
Lucent Technologies Inc.
DATA1
TQS1
(1)
Data Sheet
April 1997
R2—B0
R3—B0
DATA0
TQS0
(1)