T7115AMCD LSI, T7115AMCD Datasheet - Page 35

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Functional Description
Table 13. Register R6—Operation Control Register
* RLOOP and LLOOP should not be set to 1 simultaneously.
† Setting RRES and TRES simultaneously returns the registers to their default values without causing the outputs to 3-state.
Register
R6—B7
PDWN
(0)
R6
R6
R6
R6
R6
R6
R6
R6
R6—B6
3STATE
B0*
B1*
B5
Bit
B2
B3
B4
B6
B7
(0)
†
Symbol
3STATE
RLOOP
LLOOP
PDWN
RRES
TRES
ENR
R6—B5
ENT
(continued)
TRES
(0)
Remote Loopback. Setting this bit to 1 loops the received data back to
the distant end. When this bit is 0, normal transmission occurs.
Local Loopback. Setting this bit to 1 loops transmitted data to the inter-
nal receiver. The receive data pin input (either DRA or DRB) is ignored.
Clearing this bit to 0 allows normal transmission.
Enable Receiver. When this bit is set to 1, the received data is pro-
cessed by the receiver. When this bit is cleared to 0, incoming data is
ignored.
Enable Transmitter. When this bit is set to 1, the transmitter is enabled,
and user data is transmitted on the selected transmit data pin(s). If no
transmit data pin is selected, the transmitter empties while the output
pins are 3-stated. When this bit is cleared to 0, the transmitter is dis-
abled. See Table 3.
Receiver Reset. Write only. Setting this bit to 1 generates an internal
pulse that resets the HDLC receiver. The receive FIFO and related sta-
tus bits are cleared. The REOF, RF, RIDLE, and OVERRUN interrupts
are cleared. The receiver is placed in a known state.
Transmitter Reset. Write only. Setting this bit to 1 generates an internal
pulse that resets the HDLC transmitter. The transmit FIFO's status bits
are initialized and the transmitter enters a known state. The UNDABT
interrupt is cleared and the TE interrupt is set. TDONE is cleared in
HDLC mode and set in transparent mode.
3STATE. This bit places all HIFI-64 outputs into a high-impedance (3-
state) state. This state lasts until both
taneously.
Powerdown. Setting this bit to 1 places the HIFI-64 into a low-power
mode. This has the effect of stopping the internal data clock and results
in significantly reduced power dissipation.
R6—B4
RRES
(0)
R6—B3
ENT
T7121 HDLC Interface for ISDN (HIFI-64)
(0)
Name/Function
R6—B2
ENR
(0)
CS
and
RD
R6—B1
LLOOP
are detected low simul-
(0)
R6—B0
RLOOP
(0)
35