T7115AMCD LSI, T7115AMCD Datasheet - Page 41

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Functional Description
Table 20. Register R12—Receiver Mask Register
Table 21. Alternate Register AR12—Receiver Match Character Register
Register
Register
AR12—B7
R12—B7
AR12
RMC7
RBM7
R12
(1)
(0)
B(0—7)
B(0—7)
Bit
AR12—B6
Bit
R12—B6
RMC6
RBM6
(1)
(1)
RMC0—RMC7 Receiver Match Character. This character is used only in transparent
RBM0—RBM7 Receiver Time-Slot Bit Mask. This register allows the HIFI-64 to pro-
Symbol
Symbol
AR12—B5
R12—B5
(continued)
RBM5
RMC5
(1)
(1)
mode (TRANS, AR11—B6 = 1). When the pattern match bit (MATCH,
AR11—B5) is set to 1, the HIFI-64 searches the incoming bit stream for
the receiver match character. Data is loaded into the receive FIFO only
after this character has been identified. The bits identified as matching
the receiver match character are the first byte loaded into the receive
FIFO. The default is to search for a flag, but any character can be pro-
grammed by the user. The search for the receiver match character can
be in a sliding window fashion (ALOCT, AR11—B4 = 0) or only on byte
boundaries (ALOCT, AR11—B4 = 1).
cess some subset of each byte received. A 1 in each bit position means
the whole byte is valid data, while placing a 0 in any bit position instructs
the HIFI-64 to ignore that bit. For example, 11111111 (default) means
process the entire received byte, and 11000000 means process only the
two most significant bits.
The masking feature is available only in the TDM highway mode (i.e.,
HWYEN, R0—B7 = 1). RBM0 masks the least significant bit received (as
defined by RLBIT [R11—B6]). See Figures 8 and 9 for examples of bit
masking and subrate operation.
AR12—B4
R12—B4
RMC4
RBM4
(1)
(1)
AR12—B3
R12—B3
RBM3
RMC3
T7121 HDLC Interface for ISDN (HIFI-64)
(1)
(1)
Name/Function
Name/Function
AR12—B2
R12—B2
RBM2
RMC2
(1)
(1)
AR12—B1
R12—B1
RMC1
RBM1
(1)
(1)
AR12—B0
R12—B0
RBM0
RMC0
(1)
(0)
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