T7115AMCD LSI, T7115AMCD Datasheet - Page 64

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Appendix
Q8: The T7121 is in HDLC mode, and the software
A8:
Q9: What happens if the transmit FIFO empties out?
A9: If HDLC mode is used, letting the transmit FIFO
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views the transmit FIFO as a 32 byte x 2 FIFO.
When the TE and TDONE are enabled:
Should an abort be received? If this is expected,
is there a solution?
empty out completely will cause an underrun to
occur and an abort to be issued. Set the transmit-
ter interrupt level (R1, b[5—0]) to a large enough
level to ensure that underruns won’t occur.
1. After initializing, when the first 32 bytes
2. After writing final data into FIFO, setting TFC,
1. The setting of the TIL bits determines when
2. TDONE is asserted two TCLKs after the last
transfer to the FIFO, when is the TE alert set?
and sending out this final data, are TE and
TDONE asserted at the same time?
the TE interrupt will be issued. The TE inter-
rupt is set in HDLC mode when the chip is
reset, so as soon as the TEIE mask bit is set
to enable the TE interrupt, the interrupt will be
asserted. In normal interrupt mode, it will
remain until the interrupt register is read. In
dynamic interrupt mode (DINT = 1), the inter-
rupt will be asserted until the empty level of
the FIFO is greater than the value of the TIL
bits; i.e., the TIL bits set the number of empty
bytes (bytes available for writing) which must
be present for the TE interrupt to occur.
That is, if the TIL level is set at 32 bytes and
33 bytes are placed in the transmit FIFO,
when the first byte is read from the FIFO, the
TE interrupt will occur (32 bytes are now
empty or available to be written to).
zero of the closing flag is transmitted; TE is
asserted as indicated above. They will not
usually come at the same time.
(continued)
General Features
Q10: What happens to the highway buffers when the
A10: In this mode, the device sends out data on every
Q11: Is there any reason for resetting the receiver,
A11: Other than in the case of some type of system
Q12: Is there any problem with letting the 3-state out-
A12: This is generally not good design practice. The
Q13: Please explain block move.
A13: To use block move, BM (R0, b3) must be set to 0
TDM highway mode is not enabled?
clock. Since the device has no way of knowing
when a bit is finished, i.e., when the last full clock
period has ended (except by the start of the next
bit clock pulse), the highway transmitter remains
enabled. The output will retain the state of the
most recent bit. When multiplexing other data
onto the highway, an external driver should be
added which is enabled only during the period
when the T7121 data is on the highway.
other than at the beginning of operation?
crash, no other reason is known.
puts float?
bus might float in such a way that other devices,
including T7121, would interpret it as valid data.
and use the ALE mode. When the ALE pulse
goes low, AD6 must be a one. Then bytes are
written into the T7121 FIFO on positive-going
edges of WR, and they are read out of the T7121
FIFO when RD is low (timing of data is as shown
in Figure 22). The only limit on the number of
bytes that are read or written is that CS must be
low, and you do not want to write a full FIFO or
read an empty one. When block mode is used,
the FIFO will read or write from the first available
byte, just as in normal operation.
Lucent Technologies Inc.
Data Sheet
April 1997