S29GL512S10TFI020 Spansion Inc., S29GL512S10TFI020 Datasheet
S29GL512S10TFI020
Specifications of S29GL512S10TFI020
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S29GL512S10TFI020 Summary of contents
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GL-S MirrorBit Non-Volatile Memory Family S29GL01GS 1 Gbit S29GL512S 512 Mbit S29GL256S 256 Mbit S29GL128S 128 Mbit CMOS 3.0 Volt Core with Versatile I/O Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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... Publication Number S29GL_128S_01GS_00 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. ...
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Buffer Programming (512-bytes) Sector Erase (128 kbytes) Active Read at 5 MHz Typical Program and Erase Rates Maximum Current Consumption ...
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Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 1.1 S29GL-S Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 10.6 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Product Overview The GL-S family consists of 128-Mbit to 1Gbit, 3.0V core, Versatile I/O, non-volatile, flash memory devices. These devices have a 16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide 16 bits ...
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Address within Page Address within Write Buffer Page Write-Buffer-Line Sector The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded Algorithm Controller ...
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Software Interface 2. Address Space Maps There are several separate address spaces that may appear within the address range of the flash memory device. One address space is visible (entered) at any given time. Flash Memory Array: the main ...
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device address space is replaced by the Data Polling Status ASO. Data Polling Status will appear at every word location in the device address space. While in EA mode, only the ...
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Sector Size (kbyte) 128 Note: These tables have been condensed to show sector related information for an entire device on a single page Sectors and their address ranges that are not explicitly listed (such as SA001-SA510) have sectors starting and ...
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The original industry format was structured to work with any memory data bus width e. g. x8, x16, x32. The ID code values are traditionally byte wide but are located at ...
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All PPB Erase The Data Polling Status word appears at all word locations in the device address space. When completed the Data Polling Status ASO is exited and the device address space returns to the address ...
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2.6.5 Dynamic Protection Bits (DYB) ASO The DYB ASO contains one bit of a volatile memory array for each Sector in the device. When the DYB ASO is entered, the DYB ...
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Data Protection The device offers several features to prevent malicious or accidental erasure of any sector via hardware means. 3.1 Device Protection Methods 3.1.1 Power-Up Write Inhibit RESET#, CE#, WE#, and, OE# are ignored during Power-On Reset (POR). During ...
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3.4 Sector Protection Methods 3.4.1 Write Protect Signal If WP the lowest or highest address sector is protected from program or erase operations independent IL of any other ...
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There is no command in the Persistent Protection method to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset. The Persistent Protection method allows boot code the option ...
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3.4.6 Sector Protection States Summary Each sector can be in one of the following protection states: Unlocked – The sector is unprotected and protection can be changed by a simple ...
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If both lock bits are selected to be programmed at the same time, the operation will abort. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled and no changes to the protection scheme ...
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The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an unreasonably long time (58 million years) for a ...
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Read Operations 4.1 Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is self- timed with the same latency from CE# or address to valid data (t 4.2 Page ...
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Embedded Operations 5.1 Embedded Algorithm Controller (EAC) The EAC takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed ...
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A program operation may be suspended to allow reading of another location (not in the Line being programmed). No other program or erase operation may be started during a suspended program operation - program or erase commands will ...
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5.2.3 Automatic ECC Each 32 byte Page has a hidden ECC value. In combination with Error Detection and Correction (EDC) logic, the ECC is used to detect and correct any single ...
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Embedded in progress 5.3.1.2 Write Buffer Programming A write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (Line). Thus, a full Write Buffer Programming operation must be aligned on a Line boundary. ...
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other than the Program Buffer to Flash is written when that command is expected at the end of the word count. The write-buffer embedded programming operation can be suspended using the ...
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Figure 5.2 Write Buffer Programming Operation with Data Polling Status Notes: 1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5 this flowchart location was reached because DQ5 = 1, then ...
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Figure 5.3 Write Buffer Programming Operation with Status Register Program aborted during Write to Buffer command Notes: 1. See Table 6.1, Command Definitions on page 57 2. When Sector Address is ...
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Sequence Issue Unlock Command 1 Issue Unlock Command 2 Issue Write to Buffer Command at Sector Address Issue Number of Locations at Sector Address Example words to pgm words to ...
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Program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there must be some periods of time between resume and the ...
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The system can determine the status of the erase operation by reading the Status Register or using Data Polling. Refer to Status Register on page 38 on page 40 for more information. Once the sector erase operation has begun, the ...
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5.3.5 Erase Suspend / Erase Resume The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash ...
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ASO Exit. The following source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion flash memory software development ...
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5.3.6.6 PPB ASO The system can access the PPB ASO by issuing the PPB entry command sequence during Read Mode. This entry command does not use a sector address from the ...
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Software Reset does not affect EA mode. Reset commands are ignored once programming or erasure has begun, until the operation is complete. Software Reset does not affect outputs; it serves primarily to return to Read mode from an ASO mode ...
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Bit # 15:8 Bit Reserved Description Bit Name Reset X Status Busy Status Invalid Ready X Status Notes: 1. Bits 15 thru 8, and 0 are reserved for future use and ...
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Data Polling Status During an active Embedded Algorithm the EAC switches to the Data Polling ASO to display EA status to any read access. A single word of status information is aliased in all locations of the device address ...
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Note: 1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. 5.4.3.2 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an ...
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DQ2: Toggle Bit II Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II ...
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Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See ...
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DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a '1'. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the EAC to standby (read mode) and the Status Register failed ...
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DQ4 is RFU and should be treated as don’t care (masked) DQ3 = 1 to indicate embedded sector erase in progress DQ2 continues to toggle, independent of the ...
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After the protection error status busy period the Status Register will show the following: SR[ Valid status displayed SR[ May or may not be erase suspended after the protection error busy period SR[5] ...
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– Reads the status register and returns to WBA busy state Write Buffer Abort Reset command Status Register Clear command 5.6 Embedded Algorithm Performance Table Parameter Sector Erase Time ...
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Command State Transitions Command Current State Read and Condition Address RA Data RD - READ READ Read Protect = False READSR - (return) Table 5.8 Read Unlock Command State Transition Status Command Current Register and Read State Read Condition ...
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Table 5.10 Erase Suspend State Command Transition Command and Current State Condition Address Data ESR (1) - SR( SR( ESSR - Note: 1. State will automatically ...
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Table 5.13 Erase Suspend - Program Command State Transition Current State Command Read and Condition Address RA Data RD WC > 256 or SA ≠ SA ES_WB ES_WB WC ≤ 256 and < Write ...
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Command Software Current and Read Reset / ASO State Condition Address RA Data RD WC > 256 or SA ≠ ≤ 256 and Write ...
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Table 5.18 Lock Register State Command Transition Command Current State and Read Condition Address RA Data LRPG1 - LRPG1 LRPG - LRPG LRSR - (return) LREXT - LREXT Command and Current State Condition Address Data CFI ...
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Table 5.22 Secure Silicon Sector Program State Command Transition Command and Current State Condition Address Data SSRPG1 - WC > 256 or SA ≠ SA SSR_WB WC ≤ 256 and SA ...
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Table 5.24 Non-Volatile Protection Command State Transition Command Software Current and Read Reset / State Condition ASO Exit Address RA xh Data RD 00F0h PPB - PPB READ PPBPG1 - PPBPG1 READ SR( PPBPG PPBPG SR(7) = ...
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Current State Command Transition BLCK Table 5.9 CER Table 5.9 CFI Table 5.19 CFISR Table 5.19 DYB Table 5.26 DYBEXT Table 5.26 DYBSET Table 5.26 DYBSR Table 5.26 ER Table 5.9 ...
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Current State Command Transition PPBPG1 Table 5.24 PPBSR Table 5.24 PPD Table 5.23 PPEXT Table 5.23 PPPG Table 5.23 PPPG1 Table 5.23 PPSR Table 5.23 PS Table 5.17 PSR Table 5.17 PSSR Table 5.17 PPWB25 Table 5.23 READ Table 5.7 ...
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Software Interface Reference 6.1 Command Summary Command Sequence First (Note 1) Addr Data Read (Note Reset/ASO Exit (Notes 7, 16) 1 XXX F0 Status Register Read ...
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Command Sequence First (Note 1) Addr Data Lock Register Entry 3 555 Program (Note 15) 2 XXX Read (Note 15 Command Set Exit 2 XXX (Notes 12, 16) Reset/ASO Exit 1 XXX (Notes 7, 16) SSR Entry 3 ...
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Command Sequence First (Note 1) Addr Data Global Non-Volatile Sector Protection Freeze Command Set Definitions PPB Lock Entry 3 555 AA PPB Lock Bit Cleared 2 XXX A0 PPB Lock Status ...
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For PWDx, only one portion of the password can be programmed per each A0 command. Portions of the password must be programmed in sequential order (PWD0 - PWD3). 15. All Lock Register bits are one-time programmable. The program state ...
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Description Lower Software Bits Upper Software Bits Device ID Device ID Word Address (SA) + 0010h (SA) + 0011h (SA) + 0012h (SA) + 0013h (SA) + 0014h (SA) + 0015h ...
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Word Address (SA) + 0027h (SA) + 0028h (SA) + 0029h (SA) + 002Ah (SA) + 002Bh (SA) + 002Ch (SA) + 002Dh (SA) + 002Eh (SA) + 002Fh (SA) + 0030h (SA) + 0031h (SA) + 0032h (SA) + ...
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Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet Word Address (SA) + 0047h (SA) + 0048h (SA) + 0049h (SA) + 004Ah (SA) + 004Bh (SA) + 004Ch ...
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Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet Word Address (SA) + 0078h (SA) + 0079h Data Embedded Hardware ...
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Hardware Interface 7. Signal Descriptions 7.1 Address and Data Configuration Address and data are connected in parallel (ADP) via separate signal inputs and I/Os. 7.2 Input/Output Summary Symbol RESET# Input CE# ...
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RESET#. Since RY/BY open drain output, several RY/BY# pins can be tied together in parallel with a pull up resistor the output is Low (Busy), the device is actively erasing, programming, or ...
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Signal Protocols The following sections describe the host system interface signal behavior and timing for the 29GL-S family flash devices. 8.1 Interface States Table 8.1 describes the required value of ...
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Power Conservation Modes 8.3.1 Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High). All inputs are ignored in this state and ...
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the Write state. If CE# returns High, the interface goes to the Standby state. Back to Back accesses, in which CE# remains Low between accesses, requires an address change to ...
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Electrical Specifications 9.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground All pins (Note 1) Output Short Circuit Current Notes: 1. Minimum DC voltage on input ...
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Symbol V V Power Supply level below which re-initialization is required LKO and V RST and V VCS CC t Duration ...
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Input Signal Overshoot Figure 9.3 Maximum Negative Overshoot Waveform max IL V min IL – ...
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9.4 DC Characteristics Parameter Description I Input Load Current LI I Output Leakage Current Active Read Current CC1 Intra-Page Read Current CC2 CC V Active ...
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Capacitance Characteristics Parameter Symbol OUT C IN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A Parameter Symbol OUT C IN2 Notes: 1. Sampled, not ...
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10. Timing Specifications 10.1 Key to Switching Waveforms Waveform 10.2 AC Test Conditions Output Load Capacitance, C Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output ...
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Power On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the V device in a system should have the V the package connections (this capacitor is generally on the order of 0.1 ...
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10.3.2 Hardware (Warm) Reset During Hardware Reset (t When RESET# continues to be held at V held but not Cold Reset has not ...
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AC Characteristics 10.4.1 Asynchronous Read Operations Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t ...
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Amax-A0 CE# OE# DQ15-DQ0 Amax-A0 CE# OE# DQ15-DQ0 Note: Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access. Amax-A4 A3-A0 ...
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Asynchronous Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t OEPH t t GHWL GHWL t t ELWL ...
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Amax-A0 CE# OE# WE# DQ15-DQ0 Amax-A0 CE# OE# WE# DQ15-DQ0 February 11, 2011 S29GL_128S_01GS_00_01 ( ...
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Amax-A0 CE# OE# WE# DQ15-D0 Amax-A0 CE# OE# WE# DQ15- Figure 10.10 Write to Read (t ) Operation Timing Diagram CE tAH ...
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Figure 10.12 Read to Write (CE# Toggle) Operation Timing Diagram Amax-A0 CE# OE# WE# DQ15-A0 Parameter JEDEC Std t t WHWH1 WHWH1 t t WHWH2 WHWH2 t BUSY t SR/W t ...
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Addresses CE# OE# WE# Data RY/BY# Note program address program data, D Addresses CE# OE# WE# Data RY/BY# Note sector address (for sector erase valid address for reading status data. ...
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Figure 10.15 Data# Polling Timing Diagram (During Embedded Algorithms) Addresses CE OE# t WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status ...
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Alternate CE# Controlled Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t CEPH t 0EPH t t GHEK ...
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Amax-A0 CE# OE# WE# DQ15-D0 February 11, 2011 S29GL_128S_01GS_00_01 ( Figure 10.19 ...
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Physical Interface 11.1 56-Pin TSOP 11.1.1 Connection Diagram Notes: 1. Pin 28, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Spansion for test or other purposes and ...
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11.1.2 Physical Diagram Figure 11.2 56-Pin Thin Small Outline Package (TSOP PACKAGE TS 56 JEDEC MO-142 (B) EC SYMBOL MIN. A --- A1 0.05 A2 0.95 b1 ...
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FBGA 11.2.1 Connection Diagram A13 WE# 4 RY/BY Notes: 1. Ball E1, Do Not Use (DNU), a device internal signal is connected to the package ...
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11.2.2 Physical Diagram Figure 11.4 LAE064—64-ball Fortified Ball Grid Array (FBGA PACKAGE LAE 064 JEDEC N/A 9. 9.00 mm PACKAGE SYMBOL MIN NOM A --- ...
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Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be ...
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12. Ordering Information The ordering part number for the General Market device is formed by a valid combination of the following: S29GL01GS 10 Device Number/Description S29GL01GS, S29GL512S, S29GL256S, S29GL128S 3.0 Volt ...
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Valid Combinations The Recommended Combinations table lists configurations planned to be available in volume. The table below will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on ...
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13. Other Resources Visit www.spansion.com 13.1 Links to Software Downloads and related information on flash device support is available at http://www.spansion.com/Support/Pages/DriversSoftware.aspx Spansion low-level drivers Enhanced flash drivers Flash ...
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Revision History Section Revision 01 (February 11, 2011) Initial release Description ® GL-S MirrorBit Family ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2011 Spansion Inc. All rights reserved. Spansion and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ...