IS43DR16320B-3DBL ISSI, Integrated Silicon Solution Inc, IS43DR16320B-3DBL Datasheet - Page 16

• Manufacturer Part Number: IS43DR16320B-3DBL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16320B-3DBL

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 280mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR86400B, IS43/46DR16320B
AC and DC Logic Input Levels
Single-ended DC Input Logic Level
Single-ended AC Input logic level
AC Input Test Conditions
Notes:
1.
2.
3.
AC Input Test Signal Waveform
Differential Input AC logic level
Notes:
1.
2.
3.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
Note: Refer to Overshoot and Undershoot Specification for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
Symbol
VREF
VSWING(Max)
SLEW
Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for
falling edges as shown in the below figure.
AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP
is the complementary input signal (such as CK#, DQS#, LDQS# or UDQS#). The minimum value is equal to V IH(AC) - V IL(AC).
The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates
the voltage at which differential input signals must cross.
Refer to Overshoot and Undershoot Specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
VID(AC)
Symbol
VIX(AC)
VIH(AC)
Symbol
VIL(AC)
VIH(DC)
Symbol
VIL(DC)
Input signal maximum peak to peak swing
AC differential crosspoint voltage
AC input logic HIGH
AC input logic LOW
AC differential input voltage
Input signal minimum slew rate
Parameter
Input reference voltage
Parameter
DC input logic HIGH
DC input logic LOW
Condition
Parameter
VSSQ - Vpeak
VREF + 0.250
Min.
DDR2-400, DDR2-533
0.5*VDDQ-0.175
VDDQ + Vpeak
VREF - 0.250
Min.
VREF + 0.125
0.5
Max.
Min.
- 0.3
0.5 x VDDQ
Value
1.0
1.0
VSSQ - Vpeak
VREF + 0.200
0.5*VDDQ+0.175
Min.
VDDQ + 0.6
DDR2-667, DDR2-800
VDDQ + 0.3 V
VREF - 0.125
Max.
Max.
VDDQ + Vpeak
VREF - 0.200
Max.
Units
V/ns
V
V
Units
V
V
Units
V
V
Notes
2, 3
Notes
Units
1
1
1, 3
V
V
2
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