IS43DR16320B-3DBL ISSI, Integrated Silicon Solution Inc, IS43DR16320B-3DBL Datasheet - Page 24

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IS43DR16320B-3DBL

Manufacturer Part Number
IS43DR16320B-3DBL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
DDR2 SDRAMr
Datasheet

Specifications of IS43DR16320B-3DBL

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
280mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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IS43/46DR86400B, IS43/46DR16320B
AC Characteristics
(AC Operating Conditions Unless Otherwise Noted)
Average Periodic Refresh
Interval (-40°C ≤ Tc ≤ +85°C)
Average Periodic Refresh
Interval (+85°C < Tc ≤ +95°C)
Average Periodic Refresh
Interval (+95°C < Tc ≤ +105°C)
Period Jitter
Half Period Jitter
Cycle to Cycle Jitter
Cumulative error, 2 cycles
Cumulative error, 3 cycles
Cumulative error, 4 cycles
Cumulative error, 5 cycles
Cumulative error, 6-10 cycles
Cumulative error, 11-50 cycles
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus
11. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. (Note: tRFC depends on DRAM density)
12. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter
13. Parameter tWTR is at least two clocks independent of operation frequency.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
Input slew rate is 1 V/ns and AC timings are guaranteed for linear signal transitions.
The CK/CK# input reference level (for timing reference to CK/CK#) is the point at which CK and CK# cross the DQS/DQS# input reference level is the cross point
when in differential strobe mode; the input reference level for signals other than CK/CK#, or DQS/DQS# is VREF.
Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW.
The output timing reference voltage level is VTT.
The values tCL(Min) and tCH(Min) refer to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be
greater than the minimum specification limits for tCL and tCH.
For input frequency change during DRAM operation.
Transitions for tHZ and tLZ occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but
specify when the device is no longer driving (HZ), or begins driving (LZ).
These parameters guarantee device timing, but they are not necessarily tested on each device.
The specific requirement is that DQS and DQS# be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined
as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
When programmed in differential strobe mode, DQS is always the logic complement of DQS except when both are in high-Z.
turnaround) degrades accordingly.
stored in the MRS.
Parameter
tERR(2PER) -175
tERR(3PER) -225
tERR(4PER) -250
tERR(5PER) -250
(11-50PER)
(6-10PER)
Symbol
tJITPER
tJITDTY
tJITCC
tREFI
tREFI
tREFI
tERR
tERR
DDR2-400B
Min
-125
-125
-250
-350
-450
-5B
Max
125
125
250
175
225
250
250
350
450
7.8
3.9
3.9
-125
-125
-250
-175
-225
-250
-250
-350
-450
DDR2-533C
Min
-37C
Max
450
125
125
250
175
225
250
250
350
7.8
3.9
3.9
DDR2-667D
Min
-125
-125
-250
-175
-225
-250
-250
-350
-450
-3D
Max
125
125
250
175
225
250
250
350
450
7.8
3.9
3.9
-100
-100
-200
-150
-175
-200
-200
-300
-450
DDR2-800E
Min
-25E
Max
450
100
100
200
150
175
200
200
300
7.8
3.9
3.9
DDR2-800D Units Notes
Min
-100
-100
-200
-150
-175
-200
-200
-300
-450
-25D
Max
100
100
200
150
175
200
200
300
450
7.8
3.9
3.9
µs 18, 23
µs 18, 23
µs 18, 23
ps
ps
ps
ps
ps
ps
ps
ps
ps
22
22
22
22
22
22
22
22
22
24

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