NAND512W3A2DN6E Micron Technology Inc, NAND512W3A2DN6E Datasheet
NAND512W3A2DN6E
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NAND512W3A2DN6E Summary of contents
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... Table 1. Device summary NAND512xxA2D NAND512R3A2D NAND512R4A2D NAND512W3A2D NAND512W4A2D November 2009 512-Mbit, 1-Gbit, 528-byte/264-word page, 1.8 V/3 V, SLC NAND flash memories TSOP48 (N) VFBGA63 1.05 mm (ZA) Hardware data protection: program/erase locked during power transitions Security features – OTP area – Serial number (unique ID) Data integrity – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.7.1 6.7.2 6.7.3 6.7.4 6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6.1 7.6.2 8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 33 9 Maximum ratings ...
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... Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. NAND flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. Program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 18. ...
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NAND512xxA2D, NAND01GxxA2C List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. To extend the lifetime of NAND flash devices it is mandatory to implement an error correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A write protect pin is available to give a hardware protection against program and erase operations ...
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... V 32 pages x 8192 blocks 1.7 to 1.95 V 256+8 8K+256 x16 words words 2 I/O8-I/O15, x16 E I/O0-I/O7, x8/x16 R W NAND flash Description Timings Package Random Sequential Page Block access access program erase Max Min Typ Typ 15 µ µ ...
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... Command register 8/53 NAND512xxA2D, NAND01GxxA2C Function memory array P/E/R controller, high voltage generator Page buffer Y decoder I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 Direction I/O I/O Input Input Input Input Output Input Input Power supply Ground – – NAND flash AI07561c ...
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... NAND512xxA2D, NAND01GxxA2C Figure 3. TSOP48 connections - x8 devices NAND flash (x8 Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI07585C 9/53 ...
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Description Figure 4. VFBGA63 connections - x8 devices (top view through package 10/ ...
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... In the x16 devices the pages are split into a 256-word main area and an 8-word spare area. Refer to Bad blocks The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. ...
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Memory array organization Figure 5. Memory array organization x8 DEVICES Block = 32 pages Page = 528 bytes (512+16) 1st half page 2nd half page (256 bytes) (256 bytes) Block Page 512 bytes Page buffer, 512 bytes 512 bytes 12/53 ...
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NAND512xxA2D, NAND01GxxA2C 3 Signals description See Figure 1: Logic connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Inputs/outputs are used to input the selected address, output the data during a read operation or input a command or data ...
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Signals description 3.6 Read Enable (R) The Read Enable, R, controls the sequential data output during read operations. Data is valid t after the falling edge of R. The falling edge of R also increments the internal RLQV column address ...
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NAND512xxA2D, NAND01GxxA2C 3.11 V ground SS Ground the reference for the power supply. It must be connected to the system SS, ground. Signals description 15/53 ...
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Bus operations 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see 4.1 Command input Command input bus operations are used to give commands to the memory. Command ...
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NAND512xxA2D, NAND01GxxA2C 4.5 Write protect Write protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents ...
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Bus operations Table 8. Address definition NAND512xxA2D Address Column address A9 - A25 Page address A9 - A13 Address in block A14 - A25 Block address A8 is set Low or High by the 00h or A8 ...
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NAND512xxA2D, NAND01GxxA2C 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... Device operations 6.1 Pointer operations As the NAND flash memories contain two different areas for x16 devices and three different areas for x8 devices (see act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device ...
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NAND512xxA2D, NAND01GxxA2C Figure 7. Pointer operations for programming Address 80h I/O 00h Inputs Areas can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. Address 80h I/O 01h Inputs Areas B, ...
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Device operations 6.2.2 Page read After the random read access the page data is transferred to the page buffer in a time of t (refer to Table 21 WHBH goes High. The data can then be read out sequentially (from ...
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NAND512xxA2D, NAND01GxxA2C Figure 9. Sequential row read operations (Read busy time) RB 00h/ I/O Address inputs 01h/ 50h Command code Figure 10. Sequential row read block diagrams Read A command, x8 devices Area B Area A (2nd half Page) (1st ...
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Device operations 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number ...
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NAND512xxA2D, NAND01GxxA2C 6.4 Copy back program The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the ...
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Device operations 6.5 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists ...
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NAND512xxA2D, NAND01GxxA2C 6.7 Read status register The device contains a status register which provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. The status ...
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Device operations 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes two steps are required: 1. first use one bus write cycle to issue the Read Electronic Signature command (90h), followed by ...
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... This section gives information on the software algorithms that Numonyx recommends to implement to manage the bad blocks and extend the lifetime of the NAND device. NAND flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged ...
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... Software algorithms Table 13. NAND flash failure modes Operation Erase Program Read Figure 15. Bad block management flowchart 30/53 NAND512xxA2D, NAND01GxxA2C Procedure Block replacement Block replacement START Block Address = Block 0 Increment Block Address Update Data NO Bad Block table = FFh? YES Last NO block? YES ...
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... Error correction code An error correction code (ECC) must be implemented in the NAND flash memories to identify and correct errors in the data. In this family of devices is required the implementation of an ECC algorithm able to correct 1 bit and to detect 2 bits for every 512 bytes ...
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... Behavioral simulation models Denali software corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND flash devices, and so allow software to be developed before hardware. 7.6.2 IBIS simulations models IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers and electrical characteristics of flash devices ...
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... IO V Supply voltage DD 1. Minimum Voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins. Maximum voltage may overshoot to V Program and erase times and endurance cycles NAND flash Min Typ 200 1.5 100,000 10 Table 15: Absolute maximum ...
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... Grade 6 A 1.8 V devices ) (1 TTL GATE devices 1.8 V devices 3 V devices 1.8 V devices 3 V devices ref (1)(2) Parameter Test condition and C are not 100% tested. IN I/O NAND512xxA2D, NAND01GxxA2C NAND flash Units Min Max 1.7 1.95 V 2.7 3.6 V –40 85 ° 0.4 2 ...
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... V Output low voltage level OL I (RB) Output low current (RB supply voltage (erase and DD V LKO program lockout) 1. Leakage currents double on stacked devices. Figure 17. Equivalent testing circuit for AC characteristics measurement NAND flash (1) Test conditions t minimum Sequential RLRL read E IL, OUT Program – Erase – ...
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DC and AC parameters Table 19. DC characteristics devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (TTL), DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current ...
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NAND512xxA2D, NAND01GxxA2C Table 21. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t BLBH2 PROG ...
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DC and AC parameters Figure 18. Command Latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 19. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH W ...
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NAND512xxA2D, NAND01GxxA2C Figure 20. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 21. Sequential data output after read AC waveforms Low Low High. ...
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DC and AC parameters Figure 22. Read status register AC waveforms tCLHWH tELWH Figure 23. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to Table 12 for the values of ...
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NAND512xxA2D, NAND01GxxA2C Figure 24. Page read A/ read B operation AC waveforms CL E tWLWL 00h or Add.N I/O 01h cycle 1 Command Code tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N Add.N cycle 2 cycle ...
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DC and AC parameters Figure 25. Read C operation, one page AC waveforms Add. M I/O 50h cycle 1 RB Command Code 1. A0-A7 is the address in the spare memory area, where A0-A3 are ...
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NAND512xxA2D, NAND01GxxA2C Figure 26. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code tWLWL tWHBL Add.N Add.N Add.N N cycle 4 cycle 2 cycle 3 Address ...
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DC and AC parameters Figure 27. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 28. Reset AC waveforms ...
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NAND512xxA2D, NAND01GxxA2C Figure 29. Program/erase enable waveforms W tVHWH WP RB I/O Figure 30. Program/erase disable waveforms W tVLWH WP High RB I/O 10.1 Ready/Busy signal electrical characteristics Figure 31, Figure 32 signal. The value required for the resistor R ...
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DC and AC parameters Figure 31. Ready/Busy AC waveform Figure 32. Ready/Busy load circuit 46/53 NAND512xxA2D, NAND01GxxA2C 1.8 V device - 0 0.1 V 3.3 V device - V OL ...
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NAND512xxA2D, NAND01GxxA2C Figure 33. Resistor value versus waveform timings for Ready/Busy signal 25°C. 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations, ...
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Package mechanical 11 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in ...
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NAND512xxA2D, NAND01GxxA2C Figure 36. VFBGA63 1. +15, 0.80 mm pitch, package outline FD1 BALL "A1" Drawing is not to scale ...
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Package mechanical Table 23. VFBGA63 1. +15, 0.80 mm pitch, package mechanical data Symbol Typ 0.65 b 0.45 D 9.00 D1 4.00 D2 7.20 ddd E 11.00 E1 ...
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... NAND512xxA2D, NAND01GxxA2C 12 Ordering information Table 24. Ordering information scheme Example: Device type NAND = NAND flash memory Density 512 = 512 Mbits (1) 01G = 1 Gbit Operating voltage 1 2 Bus width x16 Family identifier A = 528-byte/ 264-word page Device options option (Chip Enable ‘care’; sequential row read enabled Chip Enable don’ ...
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Revision history 13 Revision history Table 25. Document revision history Date 06-Nov-2008 10-Feb-2009 27-Apr-2009 26-May-2009 09-Jun-2009 10-Jul-2009 25-Nov-2009 52/53 Revision 1 Initial release. Document status promoted from target specification to preliminary data. Added NAND01GxxA2C root part numbers throughout the document. ...
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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...