PIC16F688-I/SL Microchip Technology Inc., PIC16F688-I/SL Datasheet - Page 101

• Manufacturer Part Number: PIC16F688-I/SL
• Description: 14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F688-I/SL

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin SOIC-N
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.3.1
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCTL register starts
the auto-boot sequence (Figure 10-6). While the ABD
sequence takes place, the EUSART state machine is
held in Idle. On the first rising edge of the receive line,
after the Start bit, the SPBRG begins counting up using
the BRG counter clock as shown in Table 10-6. The
fifth rising edge will occur on the RX pin at the end of
the eighth bit period. At that time, an accumulated
value totaling the proper BRG period is left in
SPBRGH, SPBRG register pair, the ABDEN bit is
automatically cleared and the RCIF interrupt flag is set.
The value in the RCREG needs to be read to clear the
RCIF interrupt. RCREG content should be discarded.
When calibrating for modes that do not use the
SPBRGH register the user can verify that the SPBRG
register did not overflow by checking for 00h in the
SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 10-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
FIGURE 10-6:
© 2006 Microchip Technology Inc.
BRG Value
BRG Clock
ABDEN bit
RCIF bit
(Interrupt)
SPBRGH
RCREG
SPBRG
RX pin
RCIDL
Note 1:
Read
AUTO-BAUD DETECT
Set by User
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
XXXXh
AUTOMATIC BAUD RATE CALCULATION
0000h
Start
bit 0
XXh
XXh
Edge #1
bit 1
bit 2
Edge #2
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
TABLE 10-6:
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
bit 3
0
0
1
1
2: It is up to the user to determine that the
3: During the auto-baud process, the auto-
bit 4
Edge #3
BRGH
During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
auto-baud detection will occur on the byte
following the Break character (see
Section 10.3.2
Break”).
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system timing
and communication baud rates must be
taken into consideration when using the
Auto-Baud Detect feature.
baud counter starts counting at 1. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract 1
from the SPBRGH:SPBRG register pair.
0
1
0
1
bit 5
BRG COUNTER CLOCK RATES
bit 6
BRG Base
Edge #4
F
F
F
F
Clock
OSC
OSC
OSC
OSC
PIC16F688
bit 7
/64
/16
/16
/4
“Auto-Wake-up
Stop bit
Edge #5
DS41203C-page 99
Auto Cleared
BRG ABD
001Ch
F
F
F
F
1Ch
00h
OSC
OSC
OSC
Clock
OSC
/512
/128
/128
/32
on