PIC16F688-I/SL Microchip Technology Inc., PIC16F688-I/SL Datasheet - Page 109

• Manufacturer Part Number: PIC16F688-I/SL
• Description: 14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F688-I/SL

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin SOIC-N
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
10.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 10-9:
© 2006 Microchip Technology Inc.
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend:
Name
are
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
SYNCHRONOUS SLAVE MODE
EUSART Receive Data Register
EUSART Transmit Data Register
BRG15
SPEN
BRG7
CSRC
EUSART Synchronous Slave
Transmit
EEIE
Bit 7
EEIF
GIE
—
identical
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
BRG14
RCIDL
BRG6
ADIE
ADIF
Bit 6
PEIE
RX9
TX9
—
(see
TRISC5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
Section 10.4.1.3
TRISC4
BRG12
CREN
SCKP
BRG4
SYNC
Bit 4
INTE
C2IE
C2IF
TRISC3
ADDEN
SENDB
BRG16
BRG11
BRG3
RAIE
C1IE
Bit 3
C1IF
TRISC2
BRG10
OSFIE
OSFIF
BRGH
FERR
BRG2
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
10.4.2.2
1.
2.
3.
4.
5.
6.
7.
Bit 2
T0IF
—
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TRISC1
OERR
BRG1
BRG9
TRMT
WUE
Bit 1
INTF
TXIE
TXIF
transmission
Synchronous Slave Transmission
Set-up:
TMR1IE
TMR1IF
TRISC0
ABDEN
RX9D
BRG0
BRG8
TX9D
Bit 0
RAIF
PIC16F688
by
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
--11 1111
0000 0000
0000 0010
POR, BOR
Value on
writing
DS41203C-page 107
the
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
--11 1111
0000 0000
0000 0010
Value on
all other
Resets
Least