PIC16F688-I/SL Microchip Technology Inc., PIC16F688-I/SL Datasheet - Page 15

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PIC16F688-I/SL

Manufacturer Part Number
PIC16F688-I/SL
Description
14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F688-I/SL

A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
12
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
14-pin SOIC-N
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC16F688-I/SL
0
2.2.2.1
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
REGISTER 2-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
IRP
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
STATUS Register
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
R/W-0
RP1
STATUS: STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
(1)
R/W-0
RP0
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
R-1
TO
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits (see Section 12.0 “Instruction Set
Summary”).
R-1
PD
Note 1: Bits IRP and RP1 of the STATUS register
2: The C and DC bits operate as a Borrow
are not used by the PIC16F688 and
should be maintained as clear. Use of
these bits is not recommended, since this
may affect upward compatibility with
future products.
and Digit Borrow out bit, respectively, in
subtraction.
R/W-x
(1)
(1)
Z
x = Bit is unknown
PIC16F688
R/W-x
DC
(1)
DS41203C-page 13
R/W-x
C
(1)
bit 0

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