PIC16F688-I/SL Microchip Technology Inc., PIC16F688-I/SL Datasheet - Page 196

• Manufacturer Part Number: PIC16F688-I/SL
• Description: 14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F688-I/SL

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin SOIC-N
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F688
CONFIG Register.............................................................. 111
Configuration Bits.............................................................. 110
CPU Features ................................................................... 109
Customer Change Notification Service ............................. 197
Customer Notification Service........................................... 197
Customer Support ............................................................. 197
D
Data EEPROM Memory ...................................................... 77
Data Memory......................................................................... 7
DC and AC Characteristics
DC Characteristics
Development Support ....................................................... 139
Device Overview ................................................................... 5
E
EEADR Register ................................................................. 78
EEADR Registers................................................................ 77
EEADRH Registers ............................................................. 77
EECON1 Register ......................................................... 77, 79
EECON2 Register ............................................................... 77
EEDAT Register.................................................................. 78
EEDATH Register ............................................................... 78
Electrical Specifications .................................................... 143
Enhanced Universal Synchronous Asynchronous Receiver
Errata .................................................................................... 4
EUSART.............................................................................. 83
DS41203C-page 194
Effects of a Reset........................................................ 60
Specifications ............................................................ 159
Associated Registers .................................................. 82
Reading....................................................................... 80
Writing ......................................................................... 80
Graphs and Tables ................................................... 163
Extended and Industrial ............................................ 149
Industrial and Extended ............................................ 145
Transmitter (EUSART) ................................................ 83
Associated Registers
Asynchronous Mode ................................................... 85
Baud Rate Generator (BRG)
Synchronous Master Mode ............................... 103, 107
Synchronous Slave Mode
Baud Rate Generator.......................................... 95
12-bit Break Transmit and Receive................... 101
Associated Registers
Auto-Wake-up on Break.................................... 100
Baud Rate Generator (BRG)............................... 95
Clock Accuracy ................................................... 92
Receiver.............................................................. 88
Setting up 9-bit Mode with Address Detect......... 90
Transmitter.......................................................... 85
Auto Baud Rate Detect ....................................... 99
Baud Rate Error, Calculating .............................. 95
Baud Rates, Asynchronous Modes..................... 96
Formulas ............................................................. 95
High Baud Rate Select (BRGH Bit)..................... 95
Associated Registers
Reception.......................................................... 105
Transmission..................................................... 103
Associated Registers
Reception.......................................................... 108
Receive ....................................................... 91
Transmit ...................................................... 87
Receive ..................................................... 106
Transmit .................................................... 104
Receive ..................................................... 108
Transmit .................................................... 107
F
Fail-Safe Clock Monitor ...................................................... 31
Firmware Instructions ....................................................... 129
Flash Program Memory ...................................................... 77
Fuses. See Configuration Bits
G
General Purpose Register File ............................................. 7
I
I/O Ports.............................................................................. 33
ID Locations...................................................................... 126
In-Circuit Debugger........................................................... 127
In-Circuit Serial Programming (ICSP)............................... 127
Indirect Addressing, INDF and FSR Registers ................... 20
Instruction Format............................................................. 129
Instruction Set................................................................... 129
INTCON Register................................................................ 15
Internal Oscillator Block
Internal Sampling Switch (R
Internet Address ............................................................... 197
Interrupts........................................................................... 119
Fail-Safe Condition Clearing....................................... 31
Fail-Safe Detection ..................................................... 31
Fail-Safe Operation..................................................... 31
Reset or Wake-up from Sleep .................................... 31
ADDLW..................................................................... 131
ADDWF..................................................................... 131
ANDLW..................................................................... 131
ANDWF..................................................................... 131
BCF .......................................................................... 131
BSF........................................................................... 131
BTFSC ...................................................................... 131
BTFSS ...................................................................... 132
CALL......................................................................... 132
CLRF ........................................................................ 132
CLRW ....................................................................... 132
CLRWDT .................................................................. 132
COMF ....................................................................... 132
DECF ........................................................................ 132
DECFSZ ................................................................... 133
GOTO ....................................................................... 133
INCF ......................................................................... 133
INCFSZ..................................................................... 133
IORLW ...................................................................... 133
IORWF...................................................................... 133
MOVF ....................................................................... 134
MOVLW .................................................................... 134
MOVWF .................................................................... 134
NOP .......................................................................... 134
RETFIE ..................................................................... 135
RETLW ..................................................................... 135
RETURN................................................................... 135
RLF ........................................................................... 136
RRF .......................................................................... 136
SLEEP ...................................................................... 136
SUBLW ..................................................................... 136
SUBWF..................................................................... 137
SWAPF ..................................................................... 137
XORLW .................................................................... 137
XORWF .................................................................... 137
Summary Table ........................................................ 130
INTOSC
Transmission .................................................... 107
Specifications ........................................... 154, 155
© 2006 Microchip Technology Inc.
SS
) Impedance........................ 73