PIC16F688-I/SL Microchip Technology Inc., PIC16F688-I/SL Datasheet - Page 97

• Manufacturer Part Number: PIC16F688-I/SL
• Description: 14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F688-I/SL

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin SOIC-N
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.3
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCTL register selects 16-bit
mode.
The SPBRGH, SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In
Synchronous mode, the BRGH bit is ignored.
Table 10-3 contains the formulas for determining the
baud rate. Example 10-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 10-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 10-3:
TABLE 10-4:
© 2006 Microchip Technology Inc.
Legend:
BAUDCTL ABDOVF
RCSTA
SPBRG
SPBRGH
TXSTA
Legend:
Name
SYNC
0
0
0
0
1
1
EUSART Baud Rate Generator
(BRG)
x = Don’t care, n = value of SPBRGH, SPBRG register pair
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
BRG15
Configuration Bits
SPEN
BRG7
CSRC
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
BRG16
0
0
1
1
0
1
BRG14
RCIDL
BRG6
Bit 6
RX9
TX9
BRG13
SREN
BRG5
TXEN
BRGH
Bit 5
—
0
1
0
1
x
x
BRG12
CREN
SCKP
BRG4
SYNC
Bit 4
ADDEN
SENDB
BRG16
BRG/EUSART Mode
BRG11
16-bit/Asynchronous
16-bit/Asynchronous
BRG3
16-bit/Synchronous
8-bit/Asynchronous
8-bit/Asynchronous
Bit 3
8-bit/Synchronous
BRG10
BRGH
FERR
BRG2
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 10-1:
Bit 2
Calculated Baud Rate
For a device with F
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRG:
—
Desired Baud Rate
OERR
BRG1
BRG9
TRMT
WUE
Bit 1
Error
X
ABDEN
RX9D
BRG0
BRG8
TX9D
OSC
Bit 0
=
=
=
=
=
=
=
=
CALCULATING BAUD
RATE ERROR
Calc. Baud Rate Desired Baud Rate
------------------------------------------------------------------------------------------- -
9615
-------------------------------------------------------------------- -
64 [SPBRGH:SPBRG]
-------------------------------------------- -
Desired Baud Rate
--------------------------------------------- 1
16000000
----------------------- -
----------------------- - 1
-------------------------- -
64 25
----------------------------------
16000000
25.042
9615 9600
of 16 MHz, desired baud rate
9600
PIC16F688
64
Baud Rate Formula
9600
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0010
F
–
+
POR, BOR
F
F
F
Value on
O S C
64
Desired Baud Rate
OSC
OSC
1
OSC
=
–
F
/[64 (n+1)]
/[16 (n+1)]
OS C
25
/[4 (n+1)]
=
–
DS41203C-page 95
0.16%
–
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0010
+
Value on
all other
Resets
1