74LVC00AD Philips Semiconductors, 74LVC00AD Datasheet

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74LVC00AD

Manufacturer Part Number
74LVC00AD
Description
3.3V QUAD 2-INPUT NAND GATE
Manufacturer
Philips Semiconductors
Datasheet

Specifications of 74LVC00AD

Circuit Type
Silicon Gate
Current, Supply
40 μA
Function Type
2-Inputs
Logic Function
NAND Gate
Logic Type
CMOS
Number Of Circuits
Quad
Package Type
SO-14
Special Features
Schmitt-Trigger
Temperature, Operating, Range
-40 to +125 °C
Voltage, Supply
3.6 V
Dc
9944
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
t
C
C
PHL
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
Quad 2-input NAND gate
P
f
f
C
V
N = total load switching outputs;
L = LOW voltage level.
i
o
/t
SYMBOL
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
2
V
CC
= 25 C; t
nA
f
H
H
o
L
L
2
) = sum of the outputs.
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
I
f
= GND to V
i
N + (C
r
= t
f
2.5 ns.
PARAMETER
L
CC
INPUT
.
V
CC
2
f
o
) where:
nB
H
H
L
L
2
DESCRIPTION
The 74LVC00A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74LVC00A provides the 2-input NAND function.
D
C
V
CC
L
in W).
= 50 pF; V
= 3.3 V; notes 1 and 2 15
CONDITIONS
CC
= 3.3 V
2.1
4.0
TYPICAL
OUTPUT
Product specification
nY
H
H
H
L
74LVC00A
ns
pF
pF
UNIT

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74LVC00AD Summary of contents

Page 1

... Philips Semiconductors Quad 2-input NAND gate FEATURES 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 to 3.6 V CMOS low power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V Complies with JEDEC standard no. 8-1A ...

Page 2

... Philips Semiconductors Quad 2-input NAND gate ORDERING INFORMATION TYPE NUMBER TEMPERATURE RANGE 74LVC00AD 40 to +125 C 74LVC00ADB 40 to +125 C 74LVC00APW 40 to +125 C 74LVC00ABQ 40 to +125 C PINNING PIN SYMBOL GND PACKAGE PINS PACKAGE 14 SO14 14 SSOP14 14 TSSOP14 14 DHVQFN14 DESCRIPTION data input data input data output ...

Page 3

... Philips Semiconductors Quad 2-input NAND gate handbook, halfpage A B Fig.5 Logic diagram (one gate). RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER V supply voltage CC V input voltage I V output voltage O T operating ambient temperature amb input rise and fall times r f LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). ...

Page 4

... Philips Semiconductors Quad 2-input NAND gate DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current LI I quiescent supply current ...

Page 5

... Philips Semiconductors Quad 2-input NAND gate SYMBOL PARAMETER +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current LI I quiescent supply current CC I additional quiescent supply CC current per input pin Note 1 ...

Page 6

... Philips Semiconductors Quad 2-input NAND gate AC CHARACTERISTICS GND = 2.5 ns SYMBOL PARAMETER +85 C amb t /t propagation delay PHL PLH nA skew sk( +125 C amb t /t propagation delay PHL PLH nA skew sk(0) Notes 1. Typical value is measured Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design ...

Page 7

... Philips Semiconductors Quad 2-input NAND gate PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 ...

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