PIC32MX664F064LT-I/PT Microchip Technology Inc., PIC32MX664F064LT-I/PT Datasheet - Page 49

• Manufacturer Part Number: PIC32MX664F064LT-I/PT
• Description: 100 TQFP 12X12X1MM T/R, 100 PINS, 64KB FLASH, 32KB RAM, 80 MHZ, USB, ETHERNET, 4
• Manufacturer: Microchip Technology Inc.

Specifications of PIC32MX664F064LT-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: I2C/SPI/UART/USB
• Memory Type: Flash
• Number Of Bits: 32
• Package Type: 100-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 32K Bytes
• Speed: 80 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors.
the exception types in order of priority.
TABLE 3-3:
© 2010 Microchip Technology Inc.
Reset
DSS
DINT
NMI
Interrupt
DIB
AdEL
IBE
DBp
Sys
Bp
RI
CpU
CEU
Ov
Tr
DDBL/DDBS
AdEL
AdES
DBE
DDBL
Exception
Assertion MCLR or a Power-on Reset (POR).
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
Assertion of unmasked hardware or software interrupt signal.
EJTAG debug hardware instruction break matched.
Fetch address alignment error.
Fetch reference to protected address.
Instruction fetch bus error.
EJTAG breakpoint (execution of SDBBP instruction).
Execution of SYSCALL instruction.
Execution of BREAK instruction.
Execution of a reserved instruction.
Execution of a coprocessor instruction for a coprocessor that is not enabled.
Execution of a CorExtend instruction when CorExtend is not enabled.
Execution of an arithmetic instruction that overflowed.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
Load address alignment error.
Load reference to protected address.
Store address alignment error.
Store to protected address.
Load or store bus error.
EJTAG data hardware breakpoint matched in load data compare.
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Table 3-3
lists
Description
PIC32MX5XX/6XX/7XX
DS61156F-page 49