PIC32MX664F064LT-I/PT Microchip Technology Inc., PIC32MX664F064LT-I/PT Datasheet - Page 74

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PIC32MX664F064LT-I/PT

Manufacturer Part Number
PIC32MX664F064LT-I/PT
Description
100 TQFP 12X12X1MM T/R, 100 PINS, 64KB FLASH, 32KB RAM, 80 MHZ, USB, ETHERNET, 4
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC32MX664F064LT-I/PT

A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
85
Interface
I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
100-pin TQFP
Programmable Memory
64K Bytes
Ram Size
32K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX664F064LT-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 4-11:
Legend:
Note
5000
5010
5020
5030
5040
5050
5060
5100
5120
5130
5140
5150
5160
5200
5210
5110
1:
I2C3STAT
I2C4STAT
I2C5STAT
I2C3CON
I2C3MSK
I2C3BRG
I2C4CON
I2C4MSK
I2C4BRG
I2C5CON
I2C3TRN
I2C3RCV
I2C4ADD
I2C4TRN
I2C4RCV
I2C5DD
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP
ACKSTAT
ACKSTAT
ACKSTAT
31/15
ON
ON
ON
TRSTAT
TRSTAT
TRSTAT
30/14
FRZ
FRZ
FRZ
29/13
SIDL
SIDL
SIDL
SCLREL
SCLREL
SCLREL
28/12
STRICT
STRICT
STRICT
27/11
26/10
A10M
A10M
A10M
BCL
BCL
BCL
(1)
GCSTAT
GCSTAT
GCSTAT
DISSLW
DISSLW
DISSLW
25/9
ADD10
ADD10
ADD10
SMEN
SMEN
SMEN
24/8
Bits
IWCOL
IWCOL
IWCOL
GCEN
GCEN
GCEN
23/7
Baud Rate Generator Register
Baud Rate Generator Register
STREN
STREN
STREN
I2COV
I2COV
I2COV
22/6
ACKDT
ACKDT
ACKDT
21/5
D/A
D/A
D/A
ADD<9:0>
MSK<9:0>
ADD<9:0>
MSK<9:0>
ACKEN
ACKEN
ACKEN
Transmit Register
Transmit Register
20/4
Receive Register
Receive Register
P
P
P
RCEN
RCEN
RCEN
19/3
S
S
S
Section 12.1.1 “CLR, SET and INV Registers”
18/2
PEN
R/W
PEN
R/W
PEN
R/W
RSEN
RSEN
RSEN
17/1
RBF
RBF
RBF
16/0
SEN
SEN
SEN
TBF
TBF
TBF
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000

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