PIC32MX664F064LT-I/PT Microchip Technology Inc., PIC32MX664F064LT-I/PT Datasheet - Page 79

• Manufacturer Part Number: PIC32MX664F064LT-I/PT
• Description: 100 TQFP 12X12X1MM T/R, 100 PINS, 64KB FLASH, 32KB RAM, 80 MHZ, USB, ETHERNET, 4
• Manufacturer: Microchip Technology Inc.

Specifications of PIC32MX664F064LT-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: I2C/SPI/UART/USB
• Memory Type: Flash
• Number Of Bits: 32
• Package Type: 100-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 32K Bytes
• Speed: 80 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 4-14:
Legend:
Note
5800 SPI3CON
5810 SPI3STAT
5820
5830 SPI3BRG
5A00 SPI2CON
5A10 SPI2STAT
5A20
5A30 SPI2BRG
5C00 SPI4CON
5C10 SPI4STAT
5C20 SPI4BUF
5C30 SPI4BRG
1:
SPI3BUF
SPI2BUF
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
SPI2, SPI3 AND SPI4 REGISTER MAP
FRMEN
FRMEN
FRMEN
31/15
ON
ON
ON
—
—
—
—
—
—
—
—
—
—
—
—
FRMSYNC FRMPOL
FRMSYNC FRMPOL
FRMSYNC FRMPOL
30/14
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
DISSDO
DISSDO
DISSDO
MSSEN
MSSEN
MSSEN
28/12
—
—
—
—
—
—
—
—
—
FRMSYPW
FRMSYPW
FRMSYPW
SPIBUSY
SPIBUSY
SPIBUSY
MODE32
MODE32
MODE32
27/11
—
—
—
—
—
—
RXBUFELM<4:0>
RXBUFELM<4:0>
RXBUFELM<4:0>
(1)
MODE16
MODE16
MODE16
26/10
—
—
—
—
—
—
—
—
—
FRMCNT<2:0>
FRMCNT<2:0>
FRMCNT<2:0>
25/9
SMP
SMP
SMP
—
—
—
—
—
—
—
—
—
SPITUR
SPITUR
SPITUR
24/8
CKE
CKE
CKE
—
—
—
DATA<31:0>
DATA<31:0>
DATA<31:0>
Bits
SSEN
SRMT
SSEN
SRMT
SSEN
SRMT
23/7
—
—
—
—
—
—
—
—
—
SPIROV
SPIROV
SPIROV
22/6
CKP
CKP
CKP
—
—
—
—
—
—
—
—
—
SPIRBE
SPIRBE
SPIRBE
MSTEN
MSTEN
MSTEN
21/5
—
—
—
—
—
—
—
—
—
BRG<8:0>
BRG<8:0>
BRG<8:0>
20/4
—
—
—
—
—
—
—
—
—
—
—
—
SPITBE
SPITBE
SPITBE
19/3
STXISEL<1:0>
STXISEL<1:0>
STXISEL<1:0>
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
TXBUFELM<4:0>
TXBUFELM<4:0>
TXBUFELM<4:0>
18/2
—
—
—
—
—
—
—
—
—
SPITBF
SPITBF
SPITBF
SPIFE
SPIFE
SPIFE
17/1
SRXISEL<1:0>
SRXISEL<1:0>
SRXISEL<1:0>
—
—
—
ENHBUF 0000
ENHBUF 0000
ENHBUF 0000
SPIRBF
SPIRBF
SPIRBF
16/0
—
—
—
0000
0000
0008
0000
0000
0000
0000
0000
0000
0008
0000
0000
0000
0000
0000
0000
0008
0000
0000
0000
0000